00:00:11 so I had an idea for an esolang, what if we had something like a string-rewriting system using a list of production rules 00:00:42 that's been done a few times i think? what's yr twist on it 00:01:25 where each rule was of the form "if contents of buffer X match a CFG expression Y, rewrite contents of buffer Z with an expression W", where W can have substrings copied from some part of Y 00:02:27 might be an easier or harder way to write grammars, idk. 00:05:06 CFG might be more expressive than the usual regular... 00:05:54 although as thue shows, you only need fixed strings and one buffer to be TC 00:06:35 the idea is that if you can also include expressions for multiple buffers (i.e. a set of strings A -> a set of strings B, plus a set of subexpressions C that have to be equal among matches), then you can, for example, parse C code, populate a symbol table, and check if something is known or not at the same time. 00:07:40 ... as opposed to writing a LL(*) parser for a superset of a language, and then doing semantic analysis (is this a variable name or a type name?) to discard invalid programs. 00:08:08 -!- nooodl has quit (Quit: Ik ga weg). 00:11:46 what I'm trying to do is take a turing-tarpit (a production-based string-rewriting system like Thue) and make it into something that is somewhat easier to use... except my flavor isn't much better in that regard either. 00:16:16 -!- SingingBoyo has quit (Ping timeout: 268 seconds). 00:18:13 -!- augur has joined. 00:22:21 -!- OriginalOldMan has quit (Ping timeout: 250 seconds). 00:24:30 -!- OriginalOldMan has joined. 00:32:19 -!- augur has quit (Read error: Connection reset by peer). 00:32:27 -!- augur_ has joined. 00:35:21 -!- OriginalOldMan has quit (Ping timeout: 250 seconds). 00:43:37 -!- Phantom_Hoover has quit (Ping timeout: 240 seconds). 00:53:21 -!- Bike has quit (Ping timeout: 245 seconds). 00:57:55 -!- Bike has joined. 01:07:09 -!- oerjan has quit (Quit: leaving). 01:18:29 -!- augur_ has changed nick to augur. 01:33:14 -!- nio247 has quit (Quit: Page closed). 01:51:08 -!- nisstyre has joined. 02:21:57 -!- jconn has quit (Ping timeout: 248 seconds). 02:24:18 -!- jconn has joined. 02:29:48 -!- zzo38 has joined. 03:06:34 anyone here willing to explain to me how synchronous design in circuits works? i'm missing something easy i'm sure 03:08:41 willing, not able 03:09:12 i should have known :( 03:16:38 obligatory "just ask your question" 03:17:19 "how" 03:18:02 what do you mean by "synchronous design" 03:18:04 im probably not helpin 03:18:45 i still don't understand how you like, synchronize everything to not happen all at once. it seems probably more complicated than doing "everything" on a clock posedge 03:26:31 um I'm not sure if it's what you mean, but like 03:26:44 register -> wires and transistors and stuff -> register 03:26:56 I think the idea is like. the clock is a period of time, and during that period of time, everything in the middle is "on" 03:27:04 and happens at once 03:27:19 but of course like, the signal takes time to travel down the middle, which happens during the clock, which isn't instant 03:27:24 but like, then why would you worry about latency in an adder? 03:27:34 so like, towards the start of the clock, a wire near the end might have an interdeterminate state 03:27:37 *indeterminate 03:27:44 because the electricity hasn't propagated yet? 03:28:04 yeah that's what i'm worried about 03:28:08 and the design rules and stuff ensure that the signal propagates to the end register before the clock ends, basically. so that it's not indeterminate 03:28:27 oh, i see... 03:28:28 and so, you worry about latency because that limits how fast you can set your clock 03:28:31 that makes sense. 03:28:35 oh! yeah! 03:28:36 because you can't set your clock faster than the signal propagates? 03:28:39 ok, yeah, cool 03:28:42 I think that's right. 03:28:44 that helps 03:30:06 so I think when your FPGA thing tells you the clock rate of your design, it did the analysis and found the longest path? and then did math and stuff 03:30:23 ok well i'm not as far as that yet, i'm doing the worrying myself >_> 03:30:28 with FPGA it's more complicated though because it has these limited interconnects between different parts and it sometimes has to time-division multiplex them, i think 03:32:05 and it has to decide where to put everything 03:32:16 so it's not just adding up gate delays, but actually doing a really complex optimization problem 03:32:24 yeah i think i'm still not sure how fpgas work 03:32:39 my ide thing apparently lays things out in terms of logic gates, if only at some intermediate stage 03:33:00 anyway note that you don't need clocks for pure combinational logic 03:33:23 a pure logic gate (and any circuit of such gates with no feedback) will just have outputs that settle some amount of time after all the inputs have settled 03:33:41 right, that's why we haven't learned any clocking in class :p 03:33:46 where "settle" means that the voltage is in the "represents 0" or "represents 1" range for the logic family you're using 03:34:19 (and really there are two sets of ranges, one for inputs and one for outputs) 03:34:43 I should learn circuits by reading a lot of Lava code or something. 03:35:24 so you need clocks when you have state, because you need to say when to update the state, presumably after the combinational logic has settled 03:35:32 great, a/nother/ hdl 03:35:47 (although there are some things that have state but no clocks, like a buffer with a schmitt trigger input) 03:35:51 Bike: actually there's about six things called Lava. 03:35:58 and i have the wrong xilinx chip. 03:36:13 elliott: i'm guessing you mean the one related to circuits and haskell. who could say why i am making such a guess! 03:36:24 Bike: I mean there are multiple circuit EDSLs for Haskell called Lava. 03:36:30 What HDL do you like anyways? I didn't like them perfectly due to other problem so I made up my own idea; what kind of feature would you want for HDL, anyways? I would like to know opinion of who does too 03:36:34 there's York Lava, Kansas Lava, Chalmers Lava, probably others 03:36:35 * Bike sighs, closes everything 03:36:47 back to biology, where the code is shitty but uniform 03:36:56 ther'es a circuit edsl for scala too. what lanaguage DOESN'T have a circuit edsl at this point 03:37:00 you can imagine making a whole processor — fetch, decode, execute, memory, writeback — as pure combinational logic, but the longest gate delay path through there will be really long 03:37:09 kmc: right, right 03:37:14 which is why pipelining was invented 03:37:32 kmc: what fiora said makes this much easier for me to understand intuitively 03:37:34 Bike: anyway I like 'em because VHDL and Verilog are so noisy and the Lavas seem nice and declarative (to varying degrees, I like the one that the Reduceron is built with most because it uses observable sharing so there's a lot less noise, even if it's kinda creepy). 03:37:35 hooray 03:37:41 mnoqy: I don't know; perhaps INTERCAL? Is there one in Forth? 03:37:44 I'm just throwing out things I know now :) 03:37:44 and maybe sort of get the async stuff in neural models 03:38:21 though i think i'm pretty far from implementing "An FPGA implementation of a polychronous spiking neural network with delay adaptation", soon the brain will be mine 03:38:49 elliott: yeah verilog is pretty annoying, it just doesn't matter because i'm doing the circuitry equivalent of writing "convert fahrenheit to degrees" programs 03:39:23 I have used Verilog a little bit but I don't like it all that much; the others seem worse though. 03:39:36 i suppose i shouldn't bother asking verilog-specific questions here since nobody seems to know it 03:39:49 Bike: you can take a look at http://www.cs.york.ac.uk/fp/reduceron/memos/Memo23.txt. it's accessible even to me, person who knows nothing about circuits. maybe it'll just make you feel worse about having to use verilog though 03:39:54 my experience with verilog is using it in conjunction with an ide to write a dumb pipelined processor for a schoolcourse 03:39:55 Bike: I basically know, like, my remnants of attempts to intuitively understand it -_- 03:40:17 so i possibly have memories of a tiny bit of verilog 03:41:04 elliott: why is this already talking about clock cycles... whatever, i'm just making a fuckin adder 03:41:30 Bike: so I think the FPGA has its own clock, separate from any clocks you might built into your design 03:41:46 hmmm 03:41:48 things that look like pure combinational logic might still need to be implemented using clocks 03:41:53 because of sharing those interconnects, etc 03:42:10 there's one clock provided to me but i think others were mentioned 03:43:22 -!- nisstyre has quit (Quit: Leaving). 03:43:26 looking at the xilinx development internals has kind of soured me from learning about how the chip actually works, though >_> 03:44:46 I think you had better figure it out anyways so that it can be programmed by making a program in the FPGA to do it, so that you don't need the other computer to make it. 03:45:31 What I mean is, zzo38, that to do that (which I would like to do,, in the abstract), I would essentially have to reverse engineer a few gigabytes worth of tools, which I don't really have the expertise or will to do. 03:45:56 Ask someone else to do. 03:46:18 zzo38: Could you reverse engineer a few gigabytes worth of proprietary tools for me? 03:47:21 I don't think so, but I expect that maybe many people can try to do it together. 03:50:15 That includes anyone who has the file (I don't). 03:50:45 you can get the system free, actually. 03:50:54 free as in lack of beer, obviously 03:51:25 I don't have those FPGA though. Even if I had the program it won't help if I don't have FPGA as well. 03:52:20 you don't need the physical board to figure out how the programs work. 03:52:35 -!- Bike has quit (Quit: don't feel like it). 03:53:19 Having the physical board too would help 03:55:36 What kind of features would you intend to have in hardware programming languages? 03:57:12 To me, HWPL would be something like: TRIGGER .CLOCK SET .REGISTER TO .INPUT; or perhaps you wait it continuous instead of by edge, for example: LATCH .CLOCK SET .REGISTER TO .INPUT; CONNECT .REGISTER TO .OUTPUT; 03:57:38 What is your opinion of just this example at least? 03:58:14 meanwhile in wired http://www.wired.com/wiredenterprise/2013/09/bitcoin-homeless/ 03:59:12 Some commands might be: TRIGGER vector SET vector TO vector; LATCH bit SET vector TO vector; CONNECT vector TO vector; CONNECT vector TO vector WHEN bit; and so on. 04:03:16 "And he can beef up this daily take with Bitcoin Tapper, a mobile app that doles out about 0.000133 bitcoins a day — a couple of pennies — if he just taps on a digital icon over and over again." kill everyone 04:05:29 MODULE !D_FLIP_FLOP() {.CLOCK,.D,.Q,.NOTQ} BEGIN INPUT {.CLOCK,.D}; REGISTER .Q; OUTPUT .NOTQ; CONNECT ~.Q TO .NOTQ; TRIGGER .CLOCK SET .Q TO .D; END; Is this good? 04:06:56 Bitcoin beats the shit out of regular money 04:07:15 what does it mean that 600k homeless people in the US seems surprisingly low to me 04:07:39 mnoqy: I am just using regular money though, just Canadian coins and bills 04:08:08 zzo38: i bet it doesn't have any shit in it. you can thank bitcoin for that. 04:08:41 OK 04:14:07 -!- Bike has joined. 04:16:34 -!- augur_ has joined. 04:16:36 -!- augur has quit (Read error: Connection reset by peer). 04:18:29 "Each numeric type contains exactly one value." yeah this is grand 04:28:00 Bike: What are you refering to? 04:53:02 -!- conehead has quit (Quit: Computer has gone to sleep.). 05:02:35 -!- audioPhil_ has joined. 05:03:23 -!- audioPhil has quit (Ping timeout: 248 seconds). 05:07:10 some bytes 05:09:11 -!- epicmonkey has joined. 05:14:33 kmc: .oO( https://medium.com/funny-stuff/d7e5d14065f1 ) 05:16:21 -!- epicmonkey has quit (Ping timeout: 248 seconds). 05:17:12 that's hard to read. 05:17:34 -!- SingingBoyo has joined. 05:18:43 Only the third part is relevant. 05:18:51 -!- epicmonkey has joined. 05:19:21 to? 05:19:25 or the homelessness thing. 05:19:30 buttcoin 05:20:22 i think it's worth noting that "paid to hit a button for advertisers" is, still, pretty much an actual improvement 05:25:15 -!- lifthras1ir has changed nick to lifthrasiir. 05:51:21 neat that numpy lets you get the elements of x which are less than 4 as x[x < 4] 05:51:26 because x<4 is an array of bools 05:53:35 Ah, that is interesting, and is a good idea to use array of bools like this. 05:56:27 -!- epicmonkey has quit (Ping timeout: 260 seconds). 06:20:02 -!- hogeyui__ has joined. 06:20:31 -!- hogeyui_ has quit (Ping timeout: 240 seconds). 06:20:36 -!- rodgort` has quit (Ping timeout: 240 seconds). 06:21:33 -!- rodgort has joined. 06:25:11 -!- SingingBoyo has quit (Remote host closed the connection). 06:36:07 -!- zzo38 has quit (Remote host closed the connection). 06:48:39 -!- Sgeo has joined. 06:50:46 -!- Sgeo_ has joined. 06:51:25 -!- Sgeo has quit (Read error: Connection reset by peer). 07:17:15 -!- carado has joined. 09:11:59 -!- nooodl has joined. 09:22:31 -!- Zuu has quit (Remote host closed the connection). 09:22:36 -!- Zuu_ has joined. 09:32:42 -!- Zuu_ has changed nick to Zuu. 09:33:46 -!- augur_ has quit (Ping timeout: 245 seconds). 09:43:57 -!- Zuu has quit (Quit: Reconnecting). 09:44:03 -!- Zuu has joined. 10:08:52 -!- mnoqy has quit (Quit: hello). 11:18:57 -!- Frooxius has joined. 11:44:25 -!- Phantom_Hoover has joined. 12:08:11 -!- MindlessDrone has joined. 12:59:21 -!- conehead has joined. 13:00:26 -!- conehead has quit (Remote host closed the connection). 13:00:47 -!- conehead has joined. 14:23:26 @ask Gregor elliott kicked HackEgo on Friday, could you bring it back in the channel? Thank you! =) 14:23:26 Consider it noted. 14:23:59 Nope. Manifest destiny. 14:44:57 -!- Yonkie has quit (Ping timeout: 256 seconds). 14:52:28 -!- Nisstyre-laptop has joined. 14:55:23 -!- Nisstyre-laptop has changed nick to nisstyre. 14:58:54 Gregor: Okay =P 15:13:05 -!- augur has joined. 16:18:05 -!- augur has quit (Ping timeout: 240 seconds). 16:27:31 -!- zzo38 has joined. 16:50:35 -!- augur has joined. 17:01:08 -!- zzo38 has quit (Remote host closed the connection). 17:10:22 -!- zzo38 has joined. 17:12:20 Why did elliott kick HackEgo on Friday? 17:12:47 gone power-mad 17:13:57 it was being used for multi-bot spam :p 17:15:00 I suppose you can still access it private anyways 17:15:08 Let's see 17:15:28 Yes it still works 17:17:01 And things like `list and so on can still be typed into the channel even if HackEgo no longer responds; you will have to filter on the client-side instead, now. 17:17:45 When I told you that at first, you didn't like it; now what do you think? 17:17:52 See? 17:18:56 WHAT DO YOU THINK OF MY IDEAS NOW, ACADEMY?? MWAHAHAHAHAHA *zzo surrounded by lightning* 17:25:59 "Hopefully VIS will get it working soon, but they don't care (or know) much about linux. " ausdfahisdfnqfoiasdf 17:26:31 i didn't even know that IT people not knowing some unix was a thing. what a fool i am. 17:39:55 It's a pretty common thing TBH. 17:40:39 yeah 17:40:39 yeah. 17:40:56 i don't think this problem is even linux-specific though, so i'll have to find a windows computer to test on. siiiigh 17:44:59 i wish my department and the EECS department just shared tech support. what's the fuckin point of splitting it up 17:56:06 they don't trust each other 17:59:58 -!- AnotherTest has joined. 18:04:00 Hi 18:09:58 The computer science department, as a rule, never uses the same tech support. 18:10:30 well i mean, i want the CS department's tech support to take over everyone else's, for hopefuly obvious reasons. 18:11:20 The other departments, as a rule, never use the computer science department for tech support. 18:11:25 but whyyyyy 18:38:14 -!- epicmonkey has joined. 18:41:47 -!- Bike has quit (Ping timeout: 260 seconds). 18:49:41 -!- nisstyre has quit (Quit: Leaving). 18:51:45 What should I call the command to tell it that a label refers to a vocabulary entry? (It is like DW but it sets the internal vocabulary flag in the compiler) 19:05:07 -!- epicmonkey has quit (Ping timeout: 260 seconds). 19:20:32 -!- oerjan has joined. 19:24:44 -!- yorick has joined. 19:24:50 -!- mnoqy has joined. 19:38:02 Played Mafia IRL last night. Couldn't stop cracking up when I was maf, still managed to win that round 19:39:20 it's ok as long as it's not evil laughter 19:46:28 i hate it when other people have ideas that i'd love to have 20:01:55 -!- MindlessDrone has quit (Quit: MindlessDrone). 20:17:42 -!- epicmonkey has joined. 20:18:39 "Recommended For You" "The New Nordic Diet - from Gastronomy to Health" ... I don't know about this, Coursera. 20:22:42 the lutefisk diet, guaranteed to lose weigth as long as you eat nothing else. 20:22:48 *weight 20:27:57 Corpses shed weight pretty fast. 20:28:30 some people _may_ have claimed the word "else" is redundant there. 20:36:56 -!- Bike has joined. 20:48:40 -!- ais523 has joined. 20:50:22 can i eat lutefisk and hákarl 20:54:34 i'm sure you _can_ 20:55:00 oerjan: I was laughing when the narrator announced who was killed off 20:55:41 great narrators are awesome 20:56:42 "Tragedy is when I cut my finger. Comedy is when you fall into an open sewer and die." 20:56:58 i'm not sure I am physically capable of eating hákarl 20:57:00 it sounds scary 20:57:14 They were joking that I was definitely either mafia or really liked death 20:57:21 Did I mention Mafia won? 20:57:32 yes, you did 20:57:35 what's so scary, it's just rotten poisonous fish 20:57:44 oerjan: I have seen that quotation before 20:57:54 In a movie, that is how it is. 20:58:44 -!- zzo38 has quit (Remote host closed the connection). 20:59:00 zzo38: apparently it's "The 2,000 Year Old Man". 20:59:12 and Mel Brooks. 20:59:30 -!- AnotherTest has quit (Ping timeout: 264 seconds). 20:59:50 well, i guess he'll never know. 21:02:25 -!- Guest18414 has joined. 21:07:38 -!- Guest18414 has changed nick to AwfulProgrammer. 21:13:15 the lights in my living room are now visualizing the operation of randomly chosen "turing machines" on a finite cyclic tape 21:13:52 I wonder if there are heuristics for choosing interesting machines of this sort 21:16:24 -!- epicmonkey has quit (Ping timeout: 252 seconds). 21:18:32 Bike: it's often the case that the undergrad-run computing club has better stuff than the CS department or anyone else 21:23:01 not in terms of hardware (since it's usually hand-me-downs) but in terms of competence and entertainment value 21:26:03 -!- Bike has quit (Ping timeout: 260 seconds). 21:29:58 -!- Bike has joined. 21:30:49 kmc: the CS IT seems pretty good, they can wrangle the network printers and stuff. meanwhile the LUG is kinda stereotypical :p 21:38:11 how so 21:39:20 they had a sign up talking about how linux is better than windows because it's more secure but also just more fun 21:39:48 were they having an argument about which distro is better as you passed by? xD 21:40:28 stereotypes of linux user group: likes linux 21:40:30 i didn't stick around, was only there to buy my fpga from the ieee people 21:40:31 yes 21:43:01 anyway: «Decaf design's initiative aims for global synergy of design area's to "Green" an actual product, while seeking execution by exposure to producers and investors - San Francisco" 21:43:05 *» 21:43:55 area's 21:44:21 Bike, are they making coffe? 21:44:23 *coffee 21:45:00 sounds like they're trying to obfuscate that they haven't figured out what they're doing yet 21:45:53 they retweeted a reply i made that seemingly has nothing to do with any of that, and had already retweeted a bunch of weird stuff from strangers multiple times, so i just reported them as spam 21:45:59 this will be very effacious i'm sure 21:46:19 efficacious* i dunno i love that word 21:48:58 ecoffeacious 21:49:15 Echo-feces-ous 22:24:15 -!- S1 has joined. 22:26:38 -!- S1 has quit (Client Quit). 22:49:59 -!- carado has quit (Ping timeout: 260 seconds). 23:23:59 -!- azaq23 has joined. 23:24:03 -!- yorick has quit (Remote host closed the connection). 23:25:55 -!- zzo38 has joined. 23:28:21 -!- azaq23 has quit (Ping timeout: 245 seconds). 23:46:39 -!- nooodl_ has joined. 23:47:46 -!- nooodl has quit (Disconnected by services). 23:47:49 -!- nooodl_ has changed nick to nooodl. 23:55:32 http://c431376.r76.cf2.rackcdn.com/38376/fnins-07-00014-HTML/image_m/fnins-07-00014-t001.jpg hardest of the core 23:56:17 huh LUTs as RAM 23:56:24 what did you compile 23:56:59 not me yet :( it's a neural simulator, most of the ram is axonal properties 23:57:52 hmm, I read neural stimulator and thought you were building some kind of mind-computer interface 23:58:48 what you are seeing is just the escaped AI simulating Bike to throw us off while it conquers the world.