←2021-11-11 2021-11-12 2021-11-13→ ↑2021 ↑all
00:01:29 -!- rodgort has joined.
00:06:31 <Twingamerdudes> hello
00:22:58 <Twingamerdudes> ?
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00:37:10 <Corbin> Twingamerdudes: Hi.
00:37:13 <Corbin> Drat, too slow.
00:57:12 <esolangs> [[Bedtime]] https://esolangs.org/w/index.php?diff=89564&oldid=89249 * PixelatedStarfish * (+94) /* Operation Codes */
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01:00:33 <Twingamerdudes> hello
01:00:55 <esolangs> [[Bedtime]] https://esolangs.org/w/index.php?diff=89565&oldid=89564 * PixelatedStarfish * (+64) /* Grammar */
01:01:06 <Corbin> Twingamerdudes: Hi. Sorry to miss you the last couple times. What's up?
01:01:17 <Twingamerdudes> I'm pretty good
01:01:26 <Twingamerdudes> I made a esolang and published it on the wiki today
01:01:39 <Twingamerdudes> here is is right here https://esolangs.org/wiki/Mash
01:01:46 <Twingamerdudes> how about how
01:01:49 <Twingamerdudes> *you
01:02:00 <esolangs> [[Bedtime]] https://esolangs.org/w/index.php?diff=89566&oldid=89565 * PixelatedStarfish * (+64) /* Grammar */
01:02:25 <esolangs> [[Bedtime]] https://esolangs.org/w/index.php?diff=89567&oldid=89566 * PixelatedStarfish * (+0) /* Grammar */
01:02:51 <esolangs> [[Bedtime]] https://esolangs.org/w/index.php?diff=89568&oldid=89567 * PixelatedStarfish * (+4) /* Grammar */
01:03:18 <esolangs> [[Bedtime]] https://esolangs.org/w/index.php?diff=89569&oldid=89568 * PixelatedStarfish * (+1) /* Grammar */
01:04:32 <Corbin> Trying to figure out unfolds in Cammy. Been stuck on it for a couple days now.
01:05:41 <Twingamerdudes> oof, hope you fix it
01:08:44 <Corbin> No worries. It's not broken; languages like Cammy haven't been explored much, so I don't know how to express common algorithms and data structures yet.
01:08:55 <imode> unfolds?
01:10:10 <Twingamerdudes> ah ok
01:11:31 <Corbin> Like, on lists. Cammy has folds; given f : 1 -> X and g : Y × X -> X, we have (fold f g) : [Y] -> X. Classic simple recursion on lists.
01:12:11 <Corbin> But Cammy is total, and that makes unfolding harder to express, because traditional unfolds are not total; they can diverge and create infinitely-long lists.
01:12:44 <Twingamerdudes> alr, I can't understand any of that code above lol, but I can understand the concept I think
01:13:18 <Corbin> No worries. https://esolangs.org/wiki/Cammy might help, but probably will just be more confusing. It's okay.
01:13:43 <imode> I'm still not familiar with what an unfold is.
01:14:44 <Corbin> imode: An unfold, or anamorphism, takes a seed value and a function, and generates the (infinite) list built by repeatedly applying the function to the seed value.
01:15:23 <imode> oh, huh. that's intuitive.
01:15:32 <Twingamerdudes> ok
01:15:41 <imode> if it's total you really do have a problem.
01:16:50 <Corbin> Yep. My recent plan is to take a natural number and use it for the length of the list. Then the unfold will only take a fixed number of steps.
01:16:59 <imode> that makes sense.
01:17:10 <imode> what is `pr`.
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01:18:23 <Corbin> `pr` is primitive recursion on natural numbers. Given f : 1 -> X and g : X -> X, (pr f g) : N -> X takes a natural number, creates a seed value from f, and then applies g repeatedly to build a value.
01:18:27 <HackEso> pr`? No such file or directory
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01:18:44 <imode> ah.
01:18:47 <imode> that makes sense.
01:20:29 <Corbin> Yeah, one bite at a time, it's not so bad.
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01:32:20 <Twingamerdudes> hello
01:32:28 <Corbin> Welcome back.
01:33:59 -!- ais523 has joined.
01:34:01 <Twingamerdudes> I somehow managed to update my esolang 3 times today lol
01:34:12 <Twingamerdudes> and not for bug fixes
01:34:35 <ais523> `asm pcmpeqb mm0, mm0
01:34:37 <HackEso> 0: 0f 74 c0 pcmpeqb mm0,mm0
01:34:43 <Twingamerdudes> ?
01:34:56 <Twingamerdudes> are you guys just spamming]
01:34:58 <ais523> that's another solution to setting a 64-bit register to -1 in three bytes
01:35:06 <Twingamerdudes> ok
01:35:09 <ais523> (referring to an older conversation)
01:35:27 <ais523> so it turns out to be doable for both scalar and vector registers
01:35:49 <Twingamerdudes> alr
01:35:55 <ais523> hmm, I wonder if the push-and-immediately-pop method hits that stall bug on Intel processors
01:35:59 <ais523> might be interesting to benchmark it
01:36:24 <Twingamerdudes> well, idk if it does, I don't focus on stuff like that
01:38:31 <ais523> hmm, I wonder how long it takes with LEA
01:38:47 <ais523> `asm lea (-1), %rax
01:38:49 <HackEso> 0: 48 8d 04 25 ff ff ff ff lea 0xffffffffffffffff,%rax
01:39:13 <ais523> oh right, the bitwidths are the wrong way round
01:39:18 <esolangs> [[Mash]] M https://esolangs.org/w/index.php?diff=89570&oldid=89563 * Twingamerdudes * (+0) /* Tips */
01:40:05 <esolangs> [[Mash]] M https://esolangs.org/w/index.php?diff=89571&oldid=89570 * Twingamerdudes * (+1) /* Tips */
01:40:55 <zzo38> I am also reminded of in Z-machine (which works with 16-bit numbers), there is a way to set a register to -1 with three bytes, but Infocom didn't use it and used five bytes instead. (The way with three bytes uses the BCOM (bitwise complement) instruction. I don't know enough about 64-bit x86 to know how many bytes it is on 64-bit x86, though)
01:41:30 <Twingamerdudes> ok
01:43:12 <ais523> <oren> the six bytes {0xFC, 0122, 0131, 0xF3, 0xA4, 0xC3} are sufficient for memcpy ← on modern processors, the REP MOVSB near the end there is actually implemented by the processor using an incredibly complicated microcode function that works like standard library memcpys, switching between various algorithms based on what gives the best performance for the copy size, alignment, etc.
01:43:43 <ais523> although, it's still sometimes slower than the standard library version because the processor's branch prediction mechanism doesn't work on microcode, which slows down the startup a lot
01:44:07 <ais523> zzo38: on x86-64, most instructions take at least one more byte than they really should :-(
01:44:47 <Twingamerdudes> I do not understand a single bit hereXD
01:45:02 <Twingamerdudes> XD
01:45:44 <ais523> a quick summary is that it's quite similar to 32-bit x86, except that the bytes 0x48-0x4f are all prefixes that make an instruction 64-bit (the bottom three bits are used to change which register you're using for various fields of the instruction, doubling the number of registers available)
01:45:49 <ais523> so, e.g.
01:45:58 <ais523> `asm mov %ebx, %eax
01:45:59 <HackEso> 0: 89 d8 mov %ebx,%eax
01:46:05 <ais523> `asm mov %rbx, %rax
01:46:07 <HackEso> 0: 48 89 d8 mov %rbx,%rax
01:46:10 <ais523> `asm mov %rbx, %r8
01:46:11 <HackEso> 0: 49 89 d8 mov %rbx,%r8
01:46:12 <Twingamerdudes> ok
01:46:14 <ais523> like that
01:46:42 <ais523> if you don't have the prefix, you get 32-bit instructions which zero the top half of every register they write to (for performance reasons)
01:46:59 <ais523> this means that in 64-bit code, basically every instruction starts with a 4 nybble
01:47:00 <Twingamerdudes> ok
01:47:33 <ais523> (0x40-0x47 are also prefixes, they give you the extra registers while leaving the instruction 32/16/8-bit)
01:49:16 <ais523> this is why the solution for setting the register to -1 used push/pop, because those are 64 bits by default
01:50:38 <Corbin> ais523: Insightful. Well golfed.
01:51:37 <ais523> I think I generally prefer the vector unit instruction set to the scalar unit instruction set (although it's a bit odd that they're different)
01:52:05 <ais523> vector comparisons don't use flags, they return the comparison result in a vector, and they use the convention of true = -1, so you can zero a vector register by comparing it with itself
01:52:21 <ais523> fortunately, the 64-bit vector registers are the ones that don't use the prefix (because they got added first)
01:54:45 <ais523> `asm pcmpeqb %mm5, %mm5; pcmpeqb %xmm5, %xmm5; vpcmpeqb %xmm5, %xmm5, %xmm5; vpcmpeqb %ymm5, %ymm5, %ymm5; vpcmpeqb %xmm5, %xmm5, %k5; vcmpeqb %ymm5, %ymm5, %k5; vcmpeqb %zmm5, %zmm5, %k5
01:54:46 <HackEso> ​/tmp/asm.s: Assembler messages: \ /tmp/asm.s:1: Error: no such instruction: `vcmpeqb %ymm5,%ymm5,%k5' \ /tmp/asm.s:1: Error: no such instruction: `vcmpeqb %zmm5,%zmm5,%k5' \ /tmp/asm.s: Assembler messages: \ /tmp/asm.s:1: Error: operand size mismatch for `vpcmpeqb' \ /tmp/asm.s:1: Error: no such instruction: `vcmpeqb %ymm5,%ymm5,%k5' \ /tmp/asm.s:1: Error: no such instruction: `vcmpeqb %zmm5,%zmm5,%k5'
01:54:57 <ais523> `asm pcmpeqb %mm5, %mm5; pcmpeqb %xmm5, %xmm5; vpcmpeqb %xmm5, %xmm5, %xmm5; vpcmpeqb %ymm5, %ymm5, %ymm5
01:54:59 <HackEso> 0: 0f 74 ed pcmpeqb %mm5,%mm5 \ 3: 66 0f 74 ed pcmpeqb %xmm5,%xmm5 \ 7: c5 d1 74 ed vpcmpeqb %xmm5,%xmm5,%xmm5 \ b: c5 d5 74 ed vpcmpeqb %ymm5,%ymm5,%ymm5
01:55:06 <Twingamerdudes> asm code lol
01:55:48 <ais523> I wonder whether the AVX-512 instructions aren't programmed into `asm, or whether I got the syntax wrong
01:55:50 * sprout_ looks up
01:56:04 <ais523> (I'm not very familiar with them, I don't have an AVX-512 processor)
01:56:09 <sprout_> hmm, I am in the company of real men. maybe listen
01:56:44 <Twingamerdudes> ok
02:01:58 <ais523> `asm .byte 0x62, 0x01, 0x55, 0x08, 0x74, 0xed
02:02:00 <HackEso> 0: 62 01 vpcmpeqb %xmm29,%xmm5,(bad) \ 2: 55 push %rbp \ 3: 08 .byte 0x8 \ 4: 74 ed je 0xfffffffffffffff3
02:02:16 <ais523> oh right
02:02:31 <ais523> `asm .byte 0x62, 0x01, 0x55, 0x0d, 0x74, 0xed
02:02:33 <HackEso> 0: 62 01 vpcmpeqb %xmm29,%xmm5,(bad){%k5} \ 2: 55 push %rbp \ 3: 0d .byte 0xd \ 4: 74 ed je 0xfffffffffffffff3
02:02:38 <ais523> getting closer
02:03:17 <ais523> or, less close
02:03:48 <ais523> also that is some very weird error recovery from the disassembler
02:04:06 <ais523> `asm vpcmpeqb %xmm5, %xmm5, %k5
02:04:08 <HackEso> 0: 62 f1 55 08 74 ed vpcmpeqb %xmm5,%xmm5,%k5
02:04:17 <ais523> ah, there we go
02:04:22 <ais523> six bytes!
02:05:00 <ais523> `asm vpcmpeqb %ymm5, %ymm5, %k5
02:05:02 <HackEso> 0: 62 f1 55 28 74 ed vpcmpeqb %ymm5,%ymm5,%k5
02:05:06 <ais523> `asm vpcmpeqb %xmm5, %xmm5, %k5
02:05:07 <HackEso> 0: 62 f1 55 08 74 ed vpcmpeqb %xmm5,%xmm5,%k5
02:05:12 <ais523> `asm vpcmpeqb %zmm5, %zmm5, %k5
02:05:13 <HackEso> 0: 62 f1 55 48 74 ed vpcmpeqb %zmm5,%zmm5,%k5
02:05:28 <ais523> a complete set of set-register-to--1 instructions, probably
02:05:32 <Twingamerdudes> why is this account hackeso printing some output thing of your asm code
02:05:34 <ais523> (allowing for the ones we wrote earlier)
02:05:40 <ais523> because I asked it to
02:05:43 <ais523> it's a bot
02:05:48 <Twingamerdudes> I felt like it
02:05:48 <ais523> `echo Hello. world!
02:05:49 <HackEso> Hello. world!
02:05:53 <Twingamerdudes> cool
02:06:00 <ais523> `rev abcde
02:06:01 <HackEso> rev: cannot open abcde: No such file or directory
02:06:02 <ais523> err
02:06:03 <Twingamerdudes> `echo Hello. world
02:06:04 <HackEso> Hello. world
02:06:13 <ais523> `` echo abcde | rev
02:06:14 <HackEso> edcba
02:06:34 <Twingamerdudes> `echo I am a bot!
02:06:35 <HackEso> I am a bot!
02:06:57 <ais523> it's a useful addition to conversations because it can be used to quickly test things, or to demonstrate a point
02:07:17 <ais523> also it's better at encoding AVX-512 instructions than I am, apparently
02:07:31 <Twingamerdudes> ok
02:10:17 <ais523> I should get an up-to-date copy of AMD manuals, if/when they implement AVX-512; they're generally easier to read, especially when it comes to instruction encodings
02:10:22 <Twingamerdudes> ok
02:10:51 <Twingamerdudes> `` echo ko | rev
02:10:52 <HackEso> ok
02:11:00 <Twingamerdudes> I love playing with this bot lol
02:15:06 -!- ais523 has quit (Quit: quit).
02:22:33 <Twingamerdudes> ` echo I am a bot
02:22:34 <HackEso> ​? Permission denied
02:24:27 -!- Twingamerdudes has quit (Quit: Client closed).
02:28:36 <shachaf> ais523: Not including VEX instructions, which encode the REX bits more efficiently, if I remember correctly.
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02:32:30 <ais523> shachaf: the VEX/EVEX prefixes come with an implied 4, i.e. you don't need (and can't use) a separate REX prefix because you have 4 bits for that purpose dedicated in the VEX/EVEX
02:33:23 <ais523> although, there are two VEX prefixes, a long and a short one – only the long version has room for all four of the REX prefix bits, the other one only has one (plus one more that has a similar purpose but affects the "v" register which non-vector instructions don't have)
02:33:24 <shachaf> Right. I guess it's not exactly "more efficient", it's just "not even less efficient".
02:33:51 <ais523> so if you happen to need one of the remaining bits of the REX prefix, that can force you from the short to the long VEX prefix and cost you just as much
02:34:04 <shachaf> When I was encoding x86 instructions I stopped before VEX.
02:34:14 <shachaf> How many registers should an instruction set have?
02:34:36 <ais523> and EVEX is sort-of like a superprefix that can handle any other combination of prefixes plus a lot more of its own, at the cost of being four bytes long
02:35:13 <ais523> register count is an interesting problem because modern processors have a lot more registers internally than the instruction set supports
02:35:34 <ais523> so what you actually need isn't so much a count of registers, but a method of specifying which instructions should connect to which other instructions
02:36:02 <shachaf> Sure, I mean register names.
02:36:17 <ais523> on most processors you do that by specifying the same register number in the two instructions, but I'm not convinced that that's the best option – in many cases it doesn't matter whether they both name %rcx or both name %rdx
02:36:22 <shachaf> Unless you do something entirely different like the Mill.
02:36:48 <ais523> right, the Mill has the right general idea (although I think they should have explicit outputs and implicit inputs rather than the other way round)
02:36:49 <shachaf> Which seems pretty nice to me but I don't know about the details of implementing it.
02:37:14 <shachaf> Ah, interesting, what would that look like?
02:37:14 <ais523> the Mill's approach doesn't scale
02:37:43 <ais523> each instruction would specify the number of instructions after which the result would be used
02:38:19 <ais523> so they don't specify inputs (other than memory inputs), only where the outputs go
02:38:21 <shachaf> And if an instruction takes multiple inputs it would have multiple previous instructions pointing to it?
02:38:25 <ais523> right
02:38:42 <ais523> although, you probably want to explicitly say which argument you're pointing to
02:38:50 <shachaf> That sounds kind of awful to write for, even more than the Mill.
02:38:55 <shachaf> By hand, I mean.
02:38:55 <ais523> the biggest downside of this is that you need some way to explicitly copy an output that's going to be used more than once
02:39:08 <shachaf> What's the benefit? That you don't have to emit things if you don't use them?
02:39:10 <ais523> the upside is that it scales really well, supporting pretty much arbitrary distances
02:39:30 <ais523> because the processor doesn't need fast codepaths for all possible distances, only for the small ones
02:39:35 <ais523> err, fast datapaths
02:39:49 <shachaf> Hmm.
02:39:51 <ais523> if an instruction says "use the result 100 instructions later" then it probably doesn't matter if that's implemented in a really slow way, it'll still get tehre in time
02:40:23 <ais523> in the Mill, though, if it says "use the result from 100 instructions ago" then the processor would either need to speculatively execute a very long way forwards, or else stall in order to find the value from wherever it was
02:40:46 <shachaf> Or you'd need to have occasional forwarding instructions as it's about to fall off the belt.
02:40:53 <ais523> because you can't realistically connect every execution unit to 100 different input sources within a single cycle
02:40:53 <shachaf> Which I think is what they do?
02:41:24 <Corbin> I think that they've described a technique for bumping values to keep them on the belt, but AIUI their prototype compiler always spills to memory instead.
02:41:30 <ais523> I think they use either registers or temporary memory for that, otherwise all the forwarding instructions would slow things down too much
02:42:05 <Corbin> ISTR that the Mill specifies fast scratch memory ("scratchpad") of some sort, so spills aren't as expensive as on x86/ARM.
02:42:13 <ais523> my mental model of my antibelt is to have fast interconnects for small values, some sort of shift register for medium values, and an L1-cache-like thing for large values
02:42:30 <ais523> where by "values" I mean distances
02:42:46 <ais523> spills aren't expensive even on x86
02:43:08 <Corbin> Huh. How does that sort of p-adic connectivity come about? That is pretty interesting.
02:43:39 <ais523> the AMD Zen 2 has memory spills that are as fast as registers are; it's widely speculated that it has some sort of cache for spilled registers
02:43:49 <ais523> although, the AMD Zen 3 doesn't, probably because it isn't worth the transistors
02:43:54 <Corbin> Nifty, TIL.
02:44:25 <shachaf> Is this the thing people call "memory renaming"?
02:44:43 <ais523> Intel has a three-cycle lockout for spills, if you spill a register you can't read the memory you spilled it to for three clock cycles (although the spill is done in the background so your program can do the rest of its execution during that time)
02:45:04 <ais523> shachaf: I haven't heard of that, but it would be an obvious parallel with register renaming
02:45:50 <ais523> the main drawbacks of spills are a) the instruction needed to spill, b) the memory read/write port usage which prevents you doing memory accesses in parallel, c) polluting the L1 cache
02:46:08 <ais523> (although spills to the stack don't pollute the L1 cache much, because that gets accessed all the time anyway so it tends to naturally be in L1)
02:49:05 <ais523> anyway, if you are using the register-names method of linking instructions, x86-64's 16 seem to generally be enough in my experience, just about
02:49:26 <ais523> the main time you run low is during procedure calls, due to calling conventions being inflexible
02:50:00 <ais523> and spills by their nature tend to be in the outer loops (which generally aren't performance-sensitive) as opposed to the inner loops (which are)
02:50:13 <ais523> x86's 8 is not enough
02:51:22 <ais523> although, in order to make some loops work, it's useful to have a very cheap MOV instruction available
02:52:05 <ais523> register-register MOV is very cheap on modern processors, it takes up resources in fetch and decode but not anywhere else, the instruction's handled by the register renamer rather than the normal execute units
02:52:43 <ais523> 4/cycle throughput, 0-cycle latency
02:54:00 <ais523> that compensates for one of the issues that registers have (that if you want to be able to assign to a particular register but still have the old value around, you need a MOV – often you need to do this because registers need to have the same name on every iteration of a loop, forcing you to use a particular register for something)
02:55:34 <ais523> like, say I have a loop where, on every iteration, I call a function, then write the sum of the five most recent return values of the function into an array
02:56:00 <ais523> unless I unroll it, this is going to need a ridiculous amount of MOV to keep the register names the same on every iteration
02:56:37 <ais523> because "most recent value" and "second-most recent value" and "third-most recent value" and "fourth-most recent value" and "fifth-most recent value" all need to be in registers, and need to be moved from one of those registers to another every iteration
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03:06:02 <ais523> hmm, I decided to code it to see what a compiler did with it: https://godbolt.org/z/MossdKGeo
03:07:36 <ais523> even with 16 registers, it has to spill two, because there are only 6 call-preserved registers in the x86-64 ABI (and it needs uses three of them to remember the array length, the array location, and the loop counter)
03:08:30 <ais523> …that's clearly beatable, you could store the array end location and current array position using just two registers and save a spill
03:09:13 <ais523> actually this code is amazingly optimizable
03:09:21 <ais523> let me try it in C, to see if the compilers do any better with that
03:10:10 <shachaf> Do calling conventions need to be inflexible?
03:11:01 <shachaf> Could a compiler easily just annotate each function with some extra metadata about how many registers it wants, so callers can save fewer registers?
03:12:31 <shachaf> Also, this vaguely reminds me of https://cr.yp.to/qhasm/20050210-fxch.txt which is kind of neat.
03:13:00 <shachaf> I wonder what happens with various alternatives to registers in these sorts of situations.
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03:15:16 <ais523> looks like gcc can save the spill, but clang can't (which explains why rustc couldn't, it uses the same backend as clang): https://godbolt.org/z/6End4sY7a
03:15:56 <ais523> although, gcc makes stack space for a second spill despite not actually doing the spill
03:16:31 <ais523> <shachaf> Do calling conventions need to be inflexible? Could a compiler easily just annotate each function with some extra metadata about how many registers it wants, so callers can save fewer registers? ← I think compilers could and ought to do that, but in practice they don't
03:16:36 <ais523> I've actually been really tempted to write my own that does
03:19:54 <ais523> one interesting thing that both compilers did was to zero %rax (a call-clobbered register) before making the function call
03:20:22 <ais523> there's got to be a good reason for that, if both clang and gcc are doing it, but I don't offhand know what it is
03:20:30 <shachaf> That's the varargs convention, right?
03:20:38 <shachaf> rax stores the number of floating point registers used, or something?
03:20:41 <ais523> oh, duh, I just realised that
03:20:43 <ais523> and then saw your comment saying it
03:20:49 <shachaf> I guess f isn't varargs.
03:21:05 <ais523> it is, I forgot to put "void" in the arguments list
03:21:14 <shachaf> I think a "()" function pointer can't be used for varargs, but I'm not sure.
03:21:20 <ais523> if I do, the zeroing of %rax disappears
03:21:57 <ais523> or, well, it might not be varargs, but the compiler doesn't have any proof it isn't varargs
03:22:08 <shachaf> I thought it was allowed to assume that in this situation.
03:22:16 <shachaf> At least someone told me that once.
03:22:55 <ais523> even with --std=c11 the compiler doesn't assume it isn't varargs unless I put an explicit 'void' in there
03:23:28 <ais523> maybe this is backwards compatibility with the pre-<stdarg.h> varargs mechanism?
03:24:07 <shachaf> I guess any "()" function is sort of using a deprecated mechanism so who knows.
03:25:40 <ais523> <System V ABI> For calls that may call functions that use varargs or stdargs (prototype-less calls or calls to functions containing ellipsis (...) in the declaration) %al is used as hidden argument to specify the number of vector registers used.
03:27:12 <ais523> so I guess it's required by the standard, due to the possibility of calling a non-stdarg varargs function
03:28:54 <ais523> btw, in addition to varying the calling convention per-function to change which registers are call-preserved, I think it's useful to change it per-function in other ways
03:30:06 <ais523> such as stack alignment, and even the representation of data types (e.g. if a function is going to start by sign-extending its 16-bit arguments to 32 bits regardless, it makes sense to ask the caller to do that in case the caller can do it as a side effect of another instruction rather than needing a separate movsx instruction)
03:32:22 <ais523> although you probably need a consistent convention for function pointers
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03:44:41 <fizzie> A "() function" pointer can indeed not be used to call a varargs function.
03:45:40 <fizzie> C11 "If the expression that denotes the called function has a type that does not include a prototype -- [and if] the function is defined with a type that includes a prototype, and -- the prototype ends with an ellipsis `(, ...)` -- the behavior is undefined."
03:46:22 <shachaf> I guess C11 and the System V ABI disagree on this.
03:47:10 <fizzie> It also can't be used to call a non-varargs function that has parameters with types that are changed by default argument promotions, but that's more obvious.
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07:41:56 <b_jonas> ais523: would it be against the spirit of that exercise to store some of those five values in an xmm register, both because then you have extra call-preserved space, and because you can shift four ints in it with a shufps instruction?
07:45:22 <b_jonas> oh yeah, you also get to use the phadd instruction to add the five numbers with just three instructions instead of four
07:45:45 <b_jonas> the phaddd instruction
07:47:23 <b_jonas> (or with just paddd if you reuse both the shifted and the original version and you're writing avx2 code)
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10:09:19 <esolangs> [[Esolang:Sandbox]] https://esolangs.org/w/index.php?diff=89572&oldid=89333 * AmNow * (+28) cool
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11:06:46 <APic> Moin
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11:58:14 <esolangs> [[Special:Log/newusers]] create * CuFeNiCoZn * New user account
12:03:57 <esolangs> [[Esolang:Introduce yourself]] https://esolangs.org/w/index.php?diff=89573&oldid=89536 * CuFeNiCoZn * (+188) /* Introductions */
12:04:45 <esolangs> [[User:CuFeNiCoZn]] N https://esolangs.org/w/index.php?oldid=89574 * CuFeNiCoZn * (+9) Created page with "test test"
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12:14:07 <esolangs> [[Call/cc]] https://esolangs.org/w/index.php?diff=89575&oldid=71449 * CuFeNiCoZn * (-285) Remove subjective wording
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12:56:18 <riv> hey why dont people prove that some 1D CAs are turing complete without infinite input?
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12:56:25 <riv> its about time right?
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13:12:43 <int-e> riv: It's boring at that level of generality; any TM can be implemented by a 1D CA
13:13:02 <riv> i mean rule 30 and stuff
13:13:18 <int-e> so you mean a specific 1D CA.
13:13:24 <riv> wait i forget is rule 30 the same as rule 110
13:13:38 <riv> yes a specific one, but it could be any of them - i think only rule 30 has been looked at
13:15:44 <int-e> I thought Wolfram (and probably others before him) looked at all of them and only a few of them showed chaotic enough behavior to be plausibly TC
13:16:08 <riv> by looked at i mean.. someone actually showed its turing complete
13:18:18 <int-e> also rule 30 isn't the same as rule 110
13:23:04 <int-e> riv: anyway, why don't you do it
13:23:19 <int-e> don't leave it to people
13:24:01 <riv> i was thinking that it would be really difficult
13:25:00 <riv> basically one needs to come up with predictable gadgets inside that random mess, that seems like the hard part. then (if you have enough) you can probably just combine them to make up a language
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14:06:34 <riv> or there could be other ways? any ideas?
14:07:10 <riv> I suppose you have a big problem of dealing with having to loop over 2^n cases, if you want to brute force search for stuff
14:11:13 <esolangs> [[Bedtime]] https://esolangs.org/w/index.php?diff=89576&oldid=89569 * PixelatedStarfish * (-25) /* Grammar */
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14:38:07 <esolangs> [[KonamiCode]] https://esolangs.org/w/index.php?diff=89577&oldid=89537 * GingerIndustries * (+397) Added Turing completeness
14:38:42 <esolangs> [[KonamiCode]] M https://esolangs.org/w/index.php?diff=89578&oldid=89577 * GingerIndustries * (+12) /* Special numbers */
14:40:40 <riv> i guess you want some kind of memory cell that you can repeat
14:41:32 <riv> so ideally you would want to find 2 patterns A,B sch that some X in L[AB]+R would eventually give you back X
14:46:56 <riv> although it would be okay for these things to be sequences
14:47:15 <riv> A_i becomes A_{i+1}
14:47:32 <riv> i wonder if there are any completely different approaches
14:47:37 <riv> maybe this kind of thing is too structural
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15:37:01 <esolangs> [[Language list]] https://esolangs.org/w/index.php?diff=89579&oldid=89550 * PixelatedStarfish * (+16)
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18:09:20 <esolangs> [[Bedtime]] https://esolangs.org/w/index.php?diff=89580&oldid=89576 * PixelatedStarfish * (+20) /* Operation Codes */
18:09:37 <esolangs> [[Bedtime]] https://esolangs.org/w/index.php?diff=89581&oldid=89580 * PixelatedStarfish * (-106) /* Error Messages */
18:41:28 <esolangs> [[Bedtime]] https://esolangs.org/w/index.php?diff=89582&oldid=89581 * PixelatedStarfish * (+12) /* Operation Codes */
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20:27:25 <Twingamerdudes> hello
20:27:40 <Corbin> Afternoon.
20:28:02 <Twingamerdudes> just came back from school, I'm just vibing rn
20:30:54 <riv> hi
20:34:07 <Twingamerdudes> hello
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20:42:43 <zzo38> I had the complaint before about implicit token names in Magic: the Gathering, but it looks like they fixed this now (perhaps not in quite the same way that I did, but what they did works too).
20:43:07 <Twingamerdudes> ok
20:44:24 <riv> I don't know what implicit token names are
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20:55:32 <zzo38> When an effect creates tokens without specifying their names.
20:55:52 <riv> and what is the problem with that?
20:56:02 <riv> a name is desired?
20:57:06 <riv> have you considered using 1D CA for computation?
20:57:16 <riv> like rule 110
20:59:12 <riv> https://en.wikipedia.org/wiki/Elementary_cellular_automaton
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21:04:32 <zzo38> They already had names assigned automatically and still do, but befor, the names could previously match the names of cards even if they didn't specifically say a name of a card; now they won't match.
21:04:58 <riv> OK
21:10:20 <b_jonas> zzo38: how did they fix it?
21:10:26 <b_jonas> oh
21:11:10 <b_jonas> so the names made of subtypes no longer match the normal names?
21:11:13 <b_jonas> good
21:12:06 <b_jonas> Hollow Dogs still aren't skeletons apparently. that's the only fix I'd care about :-)
21:12:18 <b_jonas> (not quite the only)
21:15:11 <b_jonas> there's a certain rules change about multiplayer that I'd like, namely that if you resign, then you are immediately no longer allowed to make the decisions that the rules and cards call for, just like with the current rules, but most of the other effects of losing the game, like removing your cards from the game, don't happen immediately, but only the next time that state-based effects are processed
21:16:23 <b_jonas> I'd like this because you can resign any time, which is reasonable because if the player person has to leave for some reason then there's no point the rules should pretend that that they can't do that, and it makes sense that they can no longer make decisions too,
21:16:46 <b_jonas> but the part that moves objects between zones is awkward to process if it's allowed any time
21:17:53 <esolangs> [[Mash]] https://esolangs.org/w/index.php?diff=89583&oldid=89571 * Twingamerdudes * (+56) Added new comparison and fixed a example
21:19:33 <b_jonas> and state-based actions are designed for this: we don't want objects to move immediately any time when they have lethal damage, so we only move them at state-based action time.
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21:51:26 <zzo38> How can I mirror a collection of documents from Wayback archive without the JavaScripts, CSS, and other HTML commands that have been added by Wayback archive?
22:08:44 <int-e> apparently you can append id_ to the timestamp and it'll do that... http://web.archive.org/web/20211112211213id_/https://example.com/
22:09:02 <int-e> via https://github.com/hartator/wayback-machine-downloader/blob/master/lib/wayback_machine_downloader.rb#L271
22:09:31 <int-e> https://archive.org/help/wayback_api.php doesn't say anything about that
22:11:35 <fizzie> https://archive.org/post/1008502/faq-on-id_-wayback-toolbar-removal -- apparently it used to be in the FAQ, but disappeared.
22:12:10 <fizzie> A more suspicious mind might think of some collusion with the third-party sites that, for a fee, "recover" your site from archive.org, that they do still link to.
22:13:22 <int-e> Ah, it makes sense that wikipedia would want to document this kind of thing.
22:17:36 <zzo38> OK, for downloading a single file, adding "id_" works. However, I want to download an entire set of files.
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