00:01:06 -!- augur has quit (Remote host closed the connection). 00:05:46 -!- sirdancealo2 has quit (Quit: ragequit). 00:55:49 -!- azaq23 has joined. 01:04:34 happy easter egg http://178.63.82.135:9090 01:04:55 8bit lovers 01:08:21 -!- tswett has quit (Changing host). 01:08:21 -!- tswett has joined. 01:11:41 -!- spacew has quit (Ping timeout: 245 seconds). 01:26:14 -!- bengt_ has joined. 01:30:13 -!- heroux has quit (Ping timeout: 240 seconds). 01:31:04 hagb4rd: wait, is that live? 01:31:11 yep! 01:31:19 I FEEL CONNECTED TO THE WORLD 01:31:21 http://www.mottt.fm/ 01:31:22 thank you so much 01:31:26 :D 01:31:47 oh shit he's cracked 01:31:49 nice session isn't it? 01:32:09 -!- heroux has joined. 01:32:17 i hope the record goes well 01:32:58 yup it's pretty good 01:33:29 Fuck Eclipse, fuck Eclipse, I'll see your ass in Eclipse, I'll see you down in hell, Pachelbel... erm, Eclipse 01:33:35 it reminds me of the film sound of noise 01:33:51 sound of noise..sounds interesting 01:34:12 It's like the sound of music, only less musical. 01:34:59 will check it out *noted 01:35:03 thx 01:35:13 but not today 01:36:05 hagb4rd: first look for "music for one apartment and six drummers" 01:36:11 it's a short film (less than ten minutes) 01:36:32 apparently it was quite successful so they made the film on the same idea 01:36:41 ok 01:37:23 -!- hagb4rd has changed nick to hagb4rd2. 01:37:53 @tell hagb4rd hagb4rd: first look for "music for one apartment and six drummers" | the film sound of noise 01:37:53 Consider it noted. 01:38:17 -!- hagb4rd2 has changed nick to hagb4rdoux. 01:40:24 -!- heroux has quit (Ping timeout: 260 seconds). 01:41:13 -!- heroux has joined. 01:41:28 -!- Sanky has left ("."). 01:43:42 And . to you too! 01:45:05 what's "zugabend"? 01:46:59 it's a bend in a zuga 01:49:32 Arc_Koen: zugabe -> shout of encore 01:49:44 -!- heroux has quit (Ping timeout: 260 seconds). 01:49:58 ah well, my spelling was close :) 01:50:20 -!- heroux has joined. 01:50:52 zug would be train.. and abend evening :) 01:51:37 yes that's why it didn't make that much sense to me 01:51:58 except as the title of some horror movies with zombies in a train 01:51:58 nighttrain 01:52:00 *g 01:52:05 Zugzwang im Abend 01:52:10 lol 01:52:18 now to find that movie! 01:52:21 ye..stress! 01:53:23 hm.. i somehow feel like goin out and check one of tose easter-parties 01:53:39 ohhhh it's really easter 01:53:49 yep .lol 01:53:59 I was thinking about easter eggs in video games or films or that kind of stuff 01:54:02 hi Arc_Koen 01:54:07 hi 01:54:18 yea me too 01:54:33 it had some ambivalente meaning 01:55:02 no ;) 01:55:04 however 01:55:15 speak up! 01:55:23 _o/ 01:55:28 party or not? 01:56:06 what kind of party are those? 01:56:29 did some guys hid chocolate eggs all around their place and people search for them? 01:56:30 basically with girls, drugs and rocknroll 01:56:51 close enough 01:57:29 well if you don't need to wake up early tomorrow morning I'd say go for it! 01:57:41 nope i don't 01:58:45 and you? 01:58:55 no holiday? 01:59:11 or whatever you do 01:59:13 we usually just get the monday 01:59:24 ah.. k 01:59:30 where are you from? 01:59:33 kmc: 01:59:33 -!- GOMADWarrior has quit (Ping timeout: 248 seconds). 01:59:34 btw 01:59:34 @ty (.) 01:59:36 (b -> c) -> (a -> b) -> a -> c 01:59:36 france 01:59:58 and also I'm not exactly employed at the moment 02:00:00 france..cool 02:09:56 -!- heroux has quit (Ping timeout: 255 seconds). 02:11:36 hagb4rdoux: so how many people are performing? 02:11:42 -!- heroux has joined. 02:11:49 (in that easter thing I'm currently listening to) 02:11:54 -!- DHeadshot has joined. 02:17:19 I'm gonna head to bed, have a good party 02:17:26 -!- Arc_Koen has quit (Quit: The struct held his beloved integer in his strong, protecting arms, his eyes like sapphire orbs staring into her own. "W-will you... Will you union me?"). 02:20:13 -!- carado has quit (Ping timeout: 256 seconds). 02:20:47 -!- carado has joined. 02:30:25 hey, have we laughed at gprolog recently? or ever? 02:30:58 is it like gnu smalltalk 02:31:29 | ?- X #> Y, Y #> X. 02:31:31 (14584 ms) no 02:31:54 what's #> 02:31:57 The performances of GNU Prolog are very encouraging (comparable to commercial systems). 02:32:10 Phantom_Hoover: "constrain to be greater than", except that it sometimes fails for no apparent reason 02:32:15 also how does swipl compare 02:32:19 #># is the version that doesn't sometimes fail for no apparent reason, it's slower 02:32:22 and that's a gprolog extension 02:32:28 so SWI probably doesn't understand it at all 02:32:38 | ?- X1 * Y1 #= 24; X2 * Y2 #= 25. 02:32:40 X1 = _#3(1..24) 02:32:41 Y1 = _#22(1..24) ? ; 02:32:42 no 02:32:48 there's an example of "sometimes fails for no apparent reason" 02:32:50 So it takes fourteen and a half seconds to tell you that > is antireflexive? 02:32:59 Bike: yeah 02:33:02 Awesome. 02:33:05 | ?- X1 * Y1 #=# 24; X2 * Y2 #=# 25. 02:33:06 X1 = _#3(1..4:6:8:12:24@) 02:33:08 Y1 = _#22(1..4:6:8:12:24@) ? ; 02:33:09 X2 = _#3(1:5:25@) 02:33:11 Y2 = _#22(1:5:25@) 02:33:15 there's the fixed version with #=#, by the way 02:33:18 What the hell's happening there, like... is it trying every number or something 02:33:28 Bike: it's doing what I told it to do 02:33:40 find X1, Y1, X2, Y2 such that X1*Y1=24, or X2*Y2=25 02:33:50 I mean with the #> thing. 02:33:56 oh, with the #> thing 02:34:02 yeah, I'm guessing it tries every number 02:34:04 I'm slow, man 02:34:13 *Every* number? 02:34:15 That's a lot of numbers. 02:34:20 between 0 and its maxint 02:34:24 which is a bit lower than the usual maxint 02:34:33 shachaf: something something hypermegaultrafinitism 02:34:46 a "bit" lower eh?? 02:34:56 | ?- X #> Y, Y #>= X. 02:34:58 (29998 ms) no 02:35:07 the fact that that's around twice as much makes me wonder 02:35:59 Say, I thought of something. Currently, programming languages and program operation are intimately tied together. 02:36:12 If you want to write a program that works like a Python program, you have to write it in Python; you can't write it in Haskell. 02:36:51 I wonder if there's some way you could divorce language from behavior. I mean, in any programming language, you're essentially defining the behaviors of a bunch of tiny objects. 02:37:11 Well what do you mean by "language" exactly 02:37:44 Maybe you could come up with some programming language that's perfectly good at expressing Python programs, Haskell programs, C++ programs, and what have you. 02:37:57 also hilarious is "findall(X,current_atom(X),Y)." 02:38:07 Bike: I may have used it with different meanings in different places. 02:38:08 GNU Prolog only supports the use of a capped finite number of strings, ever 02:38:13 that lists the strings that have been used so far 02:38:29 that's beautiful ais 02:38:33 it contains strings like '/home/diaz/GP/src/src/BipsPl/type_inl.pl' 02:38:44 Is that Perl 02:38:49 Bike: Prolog 02:38:57 oh. but still 02:38:58 and '/build/buildd/gprolog-1.3.0/src/BipsFD/fd_bool.pl' 02:39:09 Perl is capable of handling arbitrarily many strings over the lifetime of a program 02:39:30 -!- zzo38 has joined. 02:39:32 Yeah, I just thought it would be funny if the prolog system was written in Perl. 02:39:43 also a lot of debug messages, an the like 02:39:52 Bike: Prolog doesn't look very like Perl at all 02:39:59 tswett: But I mean, it's not that hard to throw on a different parser; I imagine you mean something more interesting. 02:40:07 ais523: .pl is used for perl, isn't it? 02:40:11 oh, right 02:40:13 and also for Prolog 02:40:20 So I've learned. 02:40:24 although Perl seems to win that battle, so I use .pro for Prolog 02:40:39 .log 02:40:50 I think that one's also already taken :) 02:41:14 .pro is also already taken according to Emacs, but it clashes with something I've never heard of 02:41:25 Multiple posedge signals is OK in discrete logic, so I didn't know that it is not valid in FPGA. Is there a way to make it valid? I think some FPGA have multiple clock input? 02:42:01 Bike: yeah, I do. 02:42:12 So, uh, take a Haskell definition like this one: 02:42:16 ch = 'a' 02:42:27 zzo38: most FPGAs will work with one, complain but mostly work with two and maybe three, and fail with much more 02:42:37 basically, they have to use clock circuitry for anything that is used in posedge 02:42:44 and they have a lot more logic circuitry than clock circuitry 02:42:55 also they can't drive the same register from more than one clock 02:43:00 What's the behavior of that definition? It's to create a constant thunk of type Char that, when evaluated, yields the character 'a'. 02:43:21 I'm not sure what you just said is Haskell semantics, strictly speaking? 02:43:24 Like... what's "create". 02:43:27 yeah; and in this case, that's equivalent to making ch an alias for 'a', which is what the same line would do in Algol 02:43:35 Bike: talking about Haskell semantics in a general discussion is a bad idea 02:43:51 Well yes semantics are egh, but I mean it doesn't have to mean creating anything, does it? 02:43:51 because there are so many simplifying assumptions that are true of Haskell but not in general 02:43:52 Well, by "create" I guess I mean something like "declare the existence of" or whatever. 02:43:56 and Haskell programers act like they're always correct 02:44:07 ais523: O, so something like always@(posedge X) Z<=0; always@(posedge Y) Z<=1; is not allowed; is that what you mean? 02:44:17 zzo38: yeah, a typical FPGA physically can't implement that 02:44:19 thunks aren't part of Haskell semantics, the language doesn't guarantee lazy evaulation, only non-strict semantics 02:44:24 Yeah. 02:44:28 (Well, in that case there are race conditions too) 02:44:33 also I would probably not call that a thunk anyway, because there's no application to reduce 02:44:35 a sufficiently good synthesizer might be able to translate it into something they could implement that did the same thing, but it'd be much more complicated 02:44:42 kmc: yeah, fair enough. 02:44:48 Char is an abstract data type, so it's implementation defined 02:44:56 I'm not sure where my mind is, but I read "posedge" as "Poseidon". 02:44:56 but there's a good chance that 'a' is already in weak head-normal form 02:45:08 It declares *something* that can be queried to yield the bits and bytes representing the character 'a'. 02:45:09 actually, no it couldn't 02:45:30 you can't really get the bits and bytes 02:45:32 Bits and bytes huh. 02:45:38 if X becomes 0, Y becomes 0, X becomes 1, Y becomes 1 in that order, there's no circuitry that exists in a typical FPGA that could create a clock that could clock the register on both positive edges 02:45:46 And what querying, does haskell have querying? 02:45:54 you can't observe whether your implementation stores Char as UTF-8 or UTF-32, any more than you can observe whether it stores Int in big-endian or little-endian order 02:45:55 or, hmm 02:45:59 what if you had more than one register? 02:46:00 it's just not relevant 02:46:03 * Bike Maximum Anal 02:46:11 I'm talking about if you were to translate the definition "ch = 'a'" into C or something. 02:46:24 Bike: \ldots 02:46:29 actually, I think you could do it with four registers 02:46:35 Well in C it's an assignment. That's pretty different from a Haskell binding. 02:46:37 this is actually an interesting esoprogramming experiment 02:46:48 kmc: I don't remember what that is :( 02:47:06 \ldots is a low horizontal ellipsis, like … 02:47:11 ais523: There might be possibility; is there a program to convert "portable Verilog" into what is needed for specific FPGA or whatever is being used? 02:47:26 I think such thing might be useful if you cannot otherwise write a portable Verilog code. 02:47:33 always@(posedge X) Q[0:1]=R[0:1]+1; always@(posedge Y) R[0:1]=Q[0:1]+1; assign Z=(Q-R)[1] 02:47:36 Oh. Well maybe your bicycle is going to penetrate you and you'll just have to deal. 02:48:05 zzo38: and yes; FPGAs have custom input formats, but they all come with compilers (which tend to be very expensive) to convert portable Verilog into their own input format 02:48:11 zzo38: I guess I figured that what you'd do is just only write Verilog that works on all of the FPGAs you want to target. 02:48:14 tswett: It could create a thunk resulting in the UTF-32 encoding of 'a'. Alternately, it could create a thunk resulting in a Church numeral. 02:48:32 pikhq: indeed, but the latter behavior would be annoying if you wanted to query this thing from C. 02:48:39 tswett: well my Verity compiler outputs portable VHDL, and could be made to output portable Verilog upon similar lines 02:48:40 Yes, but it would be doable. 02:48:40 tswett: Well, I don't want to only target any specific group of FPGAs; anyways I want it to work with ASIC too, and also with simulation. 02:48:43 Even from C. 02:48:49 * pikhq has done Church numerals in C. :) 02:48:56 zzo38: you shouldn't have problems if you stick to the synthesizable subset of standard Verilog 02:49:13 ais523: O, OK, then. 02:49:33 which is a case of sticking to the circuit elements that exist in all FPGAs 02:49:36 But still, someone told me, that complicated programs will not normally be portable to diferent kind of FPGA. 02:49:38 in ASICs you have more freedom 02:49:45 and that is true, it's because complicated programs normally use libraries 02:49:52 tswett: Would it be? I thought the standard FFI let you marshal Chars? 02:49:58 and the libraries are normally written by the FPGA manufacturers and not portable at all 02:50:08 also they're normally only shipped in encrypted binary form 02:50:11 and often have DRM 02:50:24 I suppose really, all I'm getting at is "let's take C and pile features on top of it until it's Haskell". 02:50:44 zzo38: if you haven't seen it already, there's http://opencores.org/ which is an attempt to make open-source libraries for FPGAs 02:50:44 C is pretty strict. 02:50:48 -!- ludamad has joined. 02:51:09 Bike: Trust me, you can do lambda in C. Which means if you're insane you can do thunks in C. 02:51:11 also aiming for ASICs, but nobody in the open-source hardware commnity can afford those yet 02:51:20 Which means if you're freaking *crazy* you can get laziness. 02:51:22 Maybe you could do some recursive parametric types through truly sad preprocessor abuse. 02:51:32 pikhq: see any Unlambda interp in C 02:51:37 * pikhq has done all that, but not touched parametric types 02:51:46 Forth is a good programming language if you don't need to do anything that involves data. 02:51:47 You crazy. 02:51:50 ais523: I did a Lazy K interp in C. 02:51:52 -!- ludamad has left ("Leaving"). 02:52:32 ais523: Those are a few of the reasons why I don't want to be forced to use such libraries; however, if their function is known well enough, then I would hope that a way to represent the function in standard Verilog and then write a separate program, the same open-source program for all FPGA/ASIC, which takes a description and a Verilog program and modifies it to work better with the FPGA description given. 02:52:53 zzo38: I don't know if there are any open-source FPGA synthesizers 02:53:06 it's not theoretically impossible for one to be written, but the manufacturers have no interest in making it easy to do so 02:53:27 ais523: I think there are open-source FPGA synthesizers but they cannot generate FPGA bitcodes 02:53:39 that would make sense 02:53:41 ais523: I have seen OpenCores. However, I have still seen, the Amber CPU core (an ARM2 compatible core), says it is for Xilinx Spartan 6 only. 02:53:58 zzo38: that would be to do with what features of the chip it used, most likely 02:53:59 pure lazy lambda can be done in 25 lines of C :) 02:54:36 Come to think of it, I don't think it would be extremely difficult to turn Haskell into C++ or something. 02:54:37 ais523: I suppose, but I would like to be able to convert it into a portable Verilog code, so that it can work in Xilinx 7-series, and non-Xilinx, too. 02:54:46 So I guess I'm going to write all my Haskell in C++ from now on. 02:55:07 zzo38: I always aim to write portable VHDL and Verilog, except when writing drivers for specific hardware 02:55:22 and even then, the only nonportability is usually due to assuming the existence of certain pins 02:56:10 which is kind-of necessary if you're interfacing with hardware 02:56:26 normally when I want to use a particular feature of an FPGA, I write code which the synthesizers will understand as trying to use that feature 02:56:28 The program I was making suggestion of, though, would be, first it does general-purpose optimization (I think Icarus Verilog does this), and then output another Verilog program which is mostly the same as the optimized one except for certain features programmed to optimize for the FPGA description (and the delay commands could be used for further optimization?) 02:56:36 ais523: What pins, specifically? 02:56:53 zzo38: whatever pins are used by the hardware I'm interfacing with 02:57:29 ais523: Can you be more specific? 02:57:32 the Verity standard library actually contains some apparently useless code, just so that Quartus II (Altera's compiler) will infer it correctly 02:57:43 zzo38: say I want to write code to output numbers on a 7-segment display 02:57:53 I assume that the hardware has 7 pins that are actually connected to the segments of such a display 02:58:09 -!- oerjan has quit (Quit: Nite). 02:58:24 -!- Lymia has quit (Ping timeout: 264 seconds). 02:58:28 But such things seems like it is not specific to the FPGA; it seems like specific to the external hardware, isn't it? 02:58:46 zzo38: well, yes 02:58:53 but you need to give the signals names that depend on the FPGA toolchain 02:59:00 either that, or connect them to pins yourself 02:59:17 the reason we gave up on Xilinx and moved to Altera was that Xilinx wouldn't give us enough information to connect the signals to pins manually 02:59:32 whereas Altera both gave us the information we needed, and also a tool that did it automatically :) 03:00:32 However what I know about Xilinx is that for small and medium FPGAs, you don't have to pay (but you still have to register) to use their software, and it is capable of running on a VM running RedHat (someone also said it works on a VM running Ubuntu), and doesn't expire. 03:01:12 If Xilinx won't do what you said, how can I use Amber on Altera or others? 03:01:46 -!- Phantom_Hoover has quit (Read error: Connection reset by peer). 03:02:18 zzo38: I don't know 03:02:46 after spending two weeks trying to get the Xilinx toolchain to work, then calling in someone who'd used it before, then them having phoned up some friends they had at Xilinx and asking for help, and it still not working 03:02:50 we gave up and moved onto Altera 03:03:18 i'm alive, i'm alive, oh i'm alive, and how I know it! but for chips and for freedom I could die. 03:07:10 Open-source FPGA would solve these problems, but since it doesn't exist, I was thinking to make an alternative solution, where a program finds things in a Verilog program which use features of FPGA and change them to use features of other FPGA, and it also mean optimization for example if there are race conditions it can assume it doesn't care, and optimize based on that. 03:09:04 zzo38: what did you think of my code that's designed to simulate your register-driven-by-two-clocks example? 03:09:12 -!- carado has quit (Ping timeout: 264 seconds). 03:09:14 always@(posedge X) Q[0:1]=R[0:1]+1; always@(posedge Y) R[0:1]=Q[0:1]+1; assign Z=(Q-R)[1] 03:09:23 I'm not sure the syntax is correct, but if it isn't, it's likely fixable 03:09:47 that might be an interesting translation to do in a compiler 03:10:06 I've actually wondered about a VHDL/Verilog selfcompiler that translates as much of the language as possible into the synthesizable subset 03:10:07 -!- Lymia has joined. 03:10:07 -!- Lymia has quit (Changing host). 03:10:07 -!- Lymia has joined. 03:10:10 using tricks like that 03:10:35 come to think of it, that can be optimized 03:10:58 always@(posedge X) Q=R; always@(posedge Y) R=~Q; assign Z=Q^R 03:12:25 ais523: I have not thought much about this code yet, but I will print it out so that I can think about it later 03:12:43 the idea is that you have two registers, each driven by a different clock 03:12:58 and perform logical operations on them in order to combine the two clock signals 03:14:33 ais523: Yes, I did mean something like the compiler that translates as much of the language as possible into the synthesizable subset, but also make things into whatever is needed to work for the target FPGA even if the input file is a generic/portable file instead of vendor-specific. 03:15:02 zzo38: the main thing I've discovered about targeting FPGAs is that the compilers tend to be sensitive to details you wouldn't think would matter 03:15:27 What kind of details? 03:15:51 in one case, I had to create a temporary register to hold the output of a cast to unsigned, and cache it to one cycle, in VHDL 03:16:03 even though the cast is a no-op in hardware 03:16:39 if I didn't, then it couldn't correctly use the result of the cache as an index into an array; it synthesized the code, but simulated the array using registers instead of using the FPGA's block memory 03:17:02 likewise, when reading from memory, I had to read from it every cycle, it didn't like reading from it only conditionally 03:17:14 which is weird because a conditional read is implemented in hardware as always reading, then storing the read value conditionally 03:19:57 That is one reason why there should be the program to automatically convert these things to make it working 03:20:13 -!- DHeadshot has quit (Read error: Connection reset by peer). 03:20:31 -!- DHeadshot has joined. 03:26:33 Maybe they will make Icarus Verilog to do such things? 03:31:01 -!- Nisstyre-laptop has joined. 03:38:43 If you know any such things can you help Icarus Verilog development team? 03:44:31 I downloaded Icarus, but have not used it for anything serious 03:44:39 sometimes I use it to compile Verilog to VHDL so I can read it ;) 03:46:51 I suppose that is one use of it. 04:03:07 I made up the Magic: the Gathering card: All non-legendary permanents have cumulative upkeep--double your life total. At the beginning of each player's first main phase, if that player's life total exceeds one million, that player loses the game. 04:05:56 * pikhq makes a complementary card 04:06:02 zzo38: it's "precombat main phase" with current templating 04:06:10 All legendart permanents have "if you would lose the game, win the game." 04:06:11 also cumulative upkeep needs reminder text 04:06:26 pikhq: that would cause a lot of draws 04:06:30 if both players had one 04:06:32 Yes, yes it would. 04:06:44 via the infinite loop rule 04:07:07 or, hmm 04:07:24 if it's worded as a replacement effect: "if you would lose the game, you win the game instead", I'm not 100% sure what happens 04:07:43 it depends on whether the the-same-effect-can't-be-replaced-multiple-times rule would trigger 04:07:48 if it does, the replacements would cancel each other out 04:07:51 * pikhq sniggers 04:08:07 "If you would lose the game, play a subgame with your library as the deck." 04:08:15 pikhq: and? 04:08:25 Bah, who needs that to do anything. 04:08:32 Subgame's enough. 04:08:38 incidentally, the DCI banned sharharazad because someone thought up an exploit where you'd use it recursively to stall out the time in the round 04:08:43 nobody actually tried to use it 04:08:50 Keeping in mind that you can wish for cards in the supergame. 04:08:52 :D 04:08:56 but it's one of those theoretical thing that it'd make sense to shut off 04:09:00 and actually you can't any more, they changed the rule 04:09:14 Oh? 04:09:20 wishes only work on sideboards nowadays 04:09:27 That's tournament rules. 04:09:33 well, yes 04:09:36 That's not in the comprehensive rules at all. 04:09:53 but they don't work on exiled cards or supergame cards even in the comp rules, I think 04:09:55 wishes? 04:09:57 just on other cards in your collection 04:09:59 The tournament rules basically patch the rules in this case to define "cards you own outside the game" to mean your sideboard. 04:10:12 ais523: They do work on supergame cards, I've checked. 04:10:13 Sgeo: "place a card with property X from outside the game into your hand. exile this card" 04:10:16 pikhq: fair enough 04:10:17 They do not work on *exiled* cards. 04:10:30 o.O 04:10:31 Well, they do work on cards in the exile zone in a supergame. 04:10:34 Really I think it would make more sense for the "cards you own outside the game" to mean your sideboard in the standard rules, rather than patching the rules in klugy ways like that. 04:10:41 incidentally, I think the original reason for the exile was so that you wouldn't accidentally forget to put the cards back in your sideboard 04:10:46 Actually I think most of the rules are too klugy. 04:10:57 They also work on cards on the stack in a supergame. 04:11:23 Do they work only on face-up cards in a supergame, or face-down cards too? 04:11:33 They work on face-down cards too. 04:11:41 I think all that matters is who owns the card, right? 04:11:44 Yes. 04:11:48 hmm, if you aim it at a face-down card, do you have to reveal it? 04:11:56 Presumably. 04:11:56 some sort of tournament rule about not being able to cheat involving morphs 04:12:05 Actually, definitely. 04:12:08 It's changing zones. :D 04:12:09 where face-down cards have to be revealed whenever they'd no longer be face-down and in play 04:12:30 or, well, no longer in play 04:12:30 The supergame rules clearly state you have to reveal the card when it leaves the battlefield. 04:12:40 if it's face-up it's effectively in play anyway 04:12:46 *effectively revealed anyway 04:12:49 (and yes, it counts as leaving the battlefield) 04:12:52 and I don't think there are any cards with a reveal trigger 04:13:17 there's that one card in Unhinged that triggers on being read, but that isn't the same 04:13:37 Also fun: removing a card from the stack in this manner is an amazingly silly counterspell. 04:14:10 pikhq: well, only being able to target cards you own is quite the drawback on a counterspell 04:14:18 Yes. 04:14:24 It's an *amazingly* silly one. 04:14:32 it's theoretically possible it could be useful 04:14:36 but not much more than that 04:14:45 Still, I suppose it may occasionally be useful to counter your own spells in a few cases 04:14:48 there are a few spells that steal control of spells on the stack, but they're rare and hardly played 04:14:59 Especially if your opponent has modified the target or something like that 04:15:13 most of the effects both steal control and modify the target 04:15:16 rather than one or the other 04:15:26 You still own the card though. 04:15:35 We're dealing with *ownership*, not control. 04:15:44 pikhq: yeah 04:15:57 I was going on the basis that it'd be more useful to counter a spell, if you didn't control it 04:16:24 Also fun, and more potentially useful: Conspiracy works on all cards you own. 04:16:27 I have seen decent players counter their own spell, but that's because they were trying to build High Tide (a well-known Legacy combo deck) in Standard 04:16:36 And there's that one Eldrazi that wishes for any number of Eldrazi. 04:16:47 and the only legal replacement for Time Spiral is Rewind 04:17:06 pikhq: there's someone on Gatherer who wants to, some day, use that card to win using Battle of Wits in Commander 04:17:15 they've had the combo in their deck forever but never pulled it off 04:17:18 :D 04:17:31 and 167 common Eldrazi to hand, just in case 04:17:38 Do you ever play Limited format? 04:17:55 I used to, but I stopped playing Limited at much the same time I stopped playing Constructed 04:18:14 That is awesome. 04:18:27 I only play Limited format. 04:18:53 pikhq: my most memorable event from a game I watched live was some sort of crazy mill versus midrange matchup in constructed 04:18:59 I won't mind if the rules are made to be specifically for Limited. 04:19:13 where the race got very close, and the midrange player won with an empty library and a "draw a card" trigger on the stack 04:19:34 I read that some sets had cards which were banned before the set came out. I suppose those cards are designed to be used with Limited only? 04:21:35 my most memorable event from a tournament I've played was in a Time Spiral draft, where I won with Coalition Victory, twice in the same tournament 04:21:35 Do you think Magic: the Gathering rules are very klugy? 04:21:35 each time with at least one of each basic land, and at least one monocolored creature of each color 04:21:35 zzo38: sometimes they fix things 04:21:35 like getting rid of substance in favour of "at the beginning of the cleanup step2 04:21:35 *" 04:21:35 ais523: They tend to make them even more klugy though 04:21:35 but in general they seem to either have unnecessary complex rules, or cards, or both 04:21:35 Yes, in favour of "at the beginning of the cleanup step..." is better, I think; still, I don't mean rules such as substance. 04:21:35 ais523: I just kinda wish they had printed a card with substance as a joke. 04:21:44 Substance is a klugy feature of the cards that use them, not really a klugy rule, I think. 04:21:52 "Worse Bear. Substance. 2/2" 04:21:59 pikhq: the fix I'd have liked would be to define substance as "Substance is a static ability. When a card loses substance, its controller sacrifices it." 04:22:02 Strictly worse than Grizzly Bears. 04:22:10 and the reminder text would be "Substance (when CARDNAME loses substance, sacrifice it)." 04:22:30 ais523: Not bad. 04:22:58 or, in its original context, "If you play CARDNAME when you couldn't play a sorcery, it gains substance until end of turn. (When it loses substance, sacrifice it.)" 04:23:10 One rule I don't like is the state-based effects that make creatures unable to be attached to anything. 04:23:41 pikhq: it's possible to come up with situations where it's more useful than Runeclaw Bear 04:23:55 although admittedly they mostly involve pumping the Runeclaw Bear and then doing something that hurts creatures with higher power 04:24:12 * pikhq declares "screw Runeclaw" 04:24:27 We *really* needed a functional reprint of Grizzly? 04:24:29 Really guys? 04:24:29 yeah but grizzly bears can't be a creature because there are two of them 04:24:40 Eff ' 04:24:41 em 04:24:50 they decided that something that iconic needed flavour in line with modern design 04:25:07 err, modern flavour 04:25:25 same reason they don't like doing walls any more 04:25:38