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00:49:14 <esolangs> [[Esolang talk:Sandbox]] https://esolangs.org/w/index.php?diff=109336&oldid=109327 * Ais523 * (-58136) this page is not a sandbox it's for discussing the sandbox
00:50:14 <esolangs> [[Welcome To...]] M https://esolangs.org/w/index.php?diff=109337&oldid=96972 * Ais523 * (+21703) Reverted edits by [[Special:Contributions/Ais523|Ais523]] ([[User talk:Ais523|talk]]) to last revision by [[User:Page crapper from explain xkcd|Page crapper from explain xkcd]]
00:50:48 <esolangs> [[Welcome To...]] https://esolangs.org/w/index.php?diff=109338&oldid=109337 * Ais523 * (-21703) Undo revision 109337 by [[Special:Contributions/Ais523|Ais523]] ([[User talk:Ais523|talk]]) rv misclicked rollback button
00:51:17 <ais523> the thing about being able to undo vandalism in one click is that sometimes you misclick, and end up redoing vandalism in one click instead
00:51:28 <ais523> should be fixed now though
00:57:54 <shachaf> What are some interesting esoteric computer architectures that exist as far as memory models/memory ordering sorts of things?
00:58:29 <shachaf> The DEC alfalfa is well-known for being a bit ridiculous, with its split caches and probe queues and things.
00:58:55 <shachaf> I think there's some nice example of a POWER thing without multicopy atomicity which behaves surprisingly.
00:59:03 <shachaf> What are other fun examples?
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01:04:18 <zzo38> I don't know the details of how those ones are working, and cannot think of another examples at this time either
01:04:59 <ais523> x86-64 has some memory write instructions that are less atomic than usual
01:05:17 <ais523> …meaning that the sfence instruction actually has a use, even though it's normally implied
01:05:50 <ais523> I think they bypass the cache altogether and just write the cacheline to memory directly once its contents are known, so maybe they don't update the cache coherence mechanism either
01:06:29 <ais523> although I have the opposite problem with x86, I find it hard to remember precisely what guarantees it actually gives
01:07:30 <int-e> hmm is it because the answer changes every decade?
01:08:15 <shachaf> Yes, streaming stores are good, but I don't think they make x86 weirder than other architectures.
01:08:28 <ais523> ooh! GPUs have lock-step memory writes available, in which under certain circumstances multiple threads will all happen to start writing to memory at the exact same time, meaning you can get away without synchronization primitives even though it looks like they should really be required
01:09:14 <ais523> so, e.g., you can have writes from thread 1 and 2 appear as an atomic block to reads from threads 1025 and 1026
01:09:21 <shachaf> Oh, that reminds me, I saw something about the Nvidia Grace/Hopper CPU/GPU memory architecture being a little bizarro.
01:09:36 <shachaf> In the way they provide coherence across CPU and GPU.
01:09:42 <shachaf> I tried to figure out what was going on with it but I couldn't find a clear explanation.
01:10:26 <ais523> now that I think about it, it's kind-of mindblowing to imagine an atomic operation being cooperatively carried out by multiple threads
01:11:05 <shachaf> Are these actual threads, running on different cores?
01:11:26 <shachaf> I've done very little GPU programming but I think sometimes they refer to different SIMD lanes as "threads".
01:11:35 <ais523> "core" is hard to define when it comes to GPUs, it's internally somewhat SIMDy
01:12:51 <ais523> they have "blocks" which are logically like software threads, in that multiple different blocks can run concurrently and one block can run while another is suspended/blocked, but each block is made out of multiple threads
01:13:20 <ais523> and the low-level execution units handle multiple threads at the same time, but only those for which the IP is in the same position, and they don't handle a whole block at a time, just a portion of it
01:13:58 <ais523> so the data flow, arithimetic, register values, etc. are all unique to the thread, but the IP is shared even though the control flow isn't necessarily shared
01:14:53 <ais523> (you can write an if statement, but both the "then" branch and the "else" branch ends up running unless all the threads that are simultaneously executing make the same choice, and threads to which the current branch doesn't apply just wait for the IP to reach the point where they can continue to run)
01:15:29 <ais523> also I suspect that for branch-prediction reasons, even if all the threads do make the same choice, both branches end up running unless the amount of skipped code is very large, but I don't know that for certain
01:16:39 <ais523> anyway, because of this sort of thing, GPUs can work well even on problems that aren't embarrassingly parallel, but optimising for their actual execution model is weird and can be hard to get right
01:16:57 <shachaf> Are there any CPU architectures in common use that don't have coherent caches?
01:17:09 <shachaf> I should say, that have incoherent caches.
01:17:38 <ais523> I think the least coherent caches have mostly died out at this point
01:18:12 <ais523> there's a commonly used RISC processor which has a release-bit and an acquire-bit on every instruction, which implies some amount of incoherence, but probably not very much
01:18:42 <ais523> err, every instruction that accesses memory
01:18:47 <ais523> also I forget which one
01:19:19 <shachaf> acquire-release doesn't imply incoherence, does it?
01:19:26 <shachaf> Unless it's different from the usual meanings?
01:20:08 <ais523> I guess not, it could just act as a reordering barrier
01:20:23 <ais523> with the actual memory accesses always being coherent, but potentially reordered
01:21:07 <shachaf> I think "reordering" is a misleading name for the ways that CPUs can behave with memory things.
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01:21:20 <ais523> I meant reordering as in out-of-order execution with a reorder buffer
01:21:38 <shachaf> Oh, I see.
01:22:58 <ais523> I guess one issue with actually incoherent caches is how you make them coherent again in order to implement an atomic operation
01:24:26 <ais523> for incoherent writes, I guess you can just pick a write arbitrarily and set. in every cache, the value that was written by that write? from the other CPUs' points of view, it'll be as though the write arrived at that moment
01:24:49 <ais523> (this isn't sequentially consistent but works fine with acquire and release)
01:25:33 <ais523> or, hmm
01:26:59 <ais523> it's too late for me to figure this out, I think – non-atomic memory behaviour is unintuitive enough that I have trouble working it out even when I'm properly awake
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02:33:49 <int-e> `? life
02:33:52 <HackEso> ​‘Life,’ said Marvin, ‘don't talk to me about life.’
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08:25:41 <river> https://www.youtube.com/watch?v=0aJ9dAOWKYk
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09:56:51 <b_jonas> "memory write instructions that are less atomic than usual" => hmm, aren't all memory write instructions non-atomic if they need to cross a page boundary, only you don't notice that when working at C level because at C level writing words unaligned is already UB?
09:57:31 <b_jonas> at instruction level, writing and especially reading unaligned is allowed and occasionally useful, though you do have to keep in mind that it comes with a penalty
09:58:23 <b_jonas> and yes, there's also the new scatter and gather vector instructions that do multiple writes and reads resp in a way that's even more non-atomic in that it's not only non-atomic wrt other threads but also to interrupts
09:58:27 <b_jonas> and faults
10:00:00 <b_jonas> "<int-e> hmm is it because the answer [x86 guarantees] changes every decade?" => it changed in an incompatible way exactly once I think, between 286 and 386, when 386 declared that you need a taken branch between writing and executing a self-modifying instruction
10:05:47 <b_jonas> shachaf: oh don't worry, we now have powerful enoguh machines that we can just implement incoherence in very high level software if we need to. I think git can do it out of the box if you generate some sha-1 collisions, and their support for any checksum algorithm other than sha-1 is experimental. and my co-workers insist on storing lots of data not suitable for git in git repositories, though the sha-1
10:05:53 <b_jonas> collisions bother me less than that they have huge repositories and the git software makes it hard to partially clone them, unlike svn.
10:06:36 <b_jonas> and lest you say that sha-1 collision is too much here, memory also only becomes incoherent when you have an address collision.
10:06:58 <b_jonas> sure, memory addresses are shorter than sha-1 checksums, but still
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11:26:30 <esolangs> [[Listack]] M https://esolangs.org/w/index.php?diff=109339&oldid=107713 * McChuck * (+174) /* Listack: A symmetric, stackless, stack-based, concatenative language */
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12:19:50 <b_jonas> so I'm watching Technology Connections' video on CED https://www.youtube.com/playlist?list=PLv0jwu7G_DFVP0SGNlBiBtFVkV5LZ7SOU , and I realized something interesting. if you want to design a disk format, you want it fixed rotation speed so each track encodes the same amount of data, and you have a fixed minimal density that you can fit that data into (as opposed to a compromise where, say, most games are
12:19:56 <b_jonas> 320K long, but you can go past the limit to make 360K long games they just give read errors way more often), then the inner radius of your data must automatically be exactly half the outer radius of the data.
12:23:03 <b_jonas> unrelated but heck I'm not supposed to get this strong allergic symptoms until later in the summer, this very warm winter sucks
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12:49:58 <river> hi
12:59:10 <esolangs> [[Listack]] M https://esolangs.org/w/index.php?diff=109340&oldid=109339 * McChuck * (+1) /* Listack: A symmetric, stackless, stack-based, concatenative language */
13:02:27 <esolangs> [[Listack]] M https://esolangs.org/w/index.php?diff=109341&oldid=109340 * McChuck * (+84) /* Listack: A symmetric, stackless, stack-based, concatenative language */
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15:36:15 <esolangs> [[Talk:Marble Machine]] N https://esolangs.org/w/index.php?oldid=109342 * CreeperBomb * (+1748) Created page with "Alright I'm going to try to explain how this works without knowing for sure how it works, to add information, destub the article, and make it so that others can use it. All of the info comes from the presented programs. The "marble" starts in the top le
16:19:12 <b_jonas> fungot, are deciduous trees the ones that are green 12 (deci-duo) months a year?
16:19:13 <fungot> b_jonas: too bad the upgrade page is 404 and the messenger site doesn't mention the d option to ps. anmaster
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18:00:18 <esolangs> [[Befunge-with-graphics]] https://esolangs.org/w/index.php?diff=109343&oldid=72635 * KingJellyfish * (+9) /* Graphics implementation */
18:03:01 <esolangs> [[Befunge-with-graphics]] https://esolangs.org/w/index.php?diff=109344&oldid=109343 * KingJellyfish * (+294) /* Virtual Jumps */
18:03:19 <esolangs> [[Befunge-with-graphics]] https://esolangs.org/w/index.php?diff=109345&oldid=109344 * KingJellyfish * (+1) /* Future features and bug fixes */
18:03:54 <esolangs> [[Befunge-with-graphics]] https://esolangs.org/w/index.php?diff=109346&oldid=109345 * KingJellyfish * (+7) /* Virtual Jumps */
18:15:31 <esolangs> [[Var=Bar]] M https://esolangs.org/w/index.php?diff=109347&oldid=109305 * Kaveh Yousefi * (+34) Improved the diction and formatting of a few command table entries and added a hyperlink to the truth-machine article.
19:05:28 <esolangs> [[Talk:Cedar--]] N https://esolangs.org/w/index.php?oldid=109348 * Joaozin003 * (+116) Created page with "== The syntax is good, to be honest! == Yeah. Pretty normal syntax, although <code>exclude</code> is a bit unusual."
19:05:36 <esolangs> [[Talk:Cedar--]] https://esolangs.org/w/index.php?diff=109349&oldid=109348 * Joaozin003 * (+88) /* The syntax is good, to be honest! */
19:37:22 <esolangs> [[Befunge-with-graphics]] https://esolangs.org/w/index.php?diff=109350&oldid=109346 * KingJellyfish * (-145) /* Event handling */
19:38:00 <esolangs> [[Befunge-with-graphics]] https://esolangs.org/w/index.php?diff=109351&oldid=109350 * KingJellyfish * (+33) /* Event handling */
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20:30:13 <Sgeo> When, exactly, is (a^b)^c = a^(b*c) valid and when is it invalid? It's certainly invalid for b=1/2 and c=2 when a is negative
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20:59:22 <esolangs> [[]] https://esolangs.org/w/index.php?diff=109352&oldid=88046 * RocketRace * (+92) Disambiguate!
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21:05:51 <esolangs> [[User:RocketRace]] https://esolangs.org/w/index.php?diff=109353&oldid=100136 * RocketRace * (+0) TFLite is actually pretty fun
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