←2013-09-20 2013-09-21 2013-09-22→ ↑2013 ↑all
00:00:11 <nio247> so I had an idea for an esolang, what if we had something like a string-rewriting system using a list of production rules
00:00:42 <mnoqy> that's been done a few times i think? what's yr twist on it
00:01:25 <nio247> where each rule was of the form "if contents of buffer X match a CFG expression Y, rewrite contents of buffer Z with an expression W", where W can have substrings copied from some part of Y
00:02:27 <nio247> might be an easier or harder way to write grammars, idk.
00:05:06 <oerjan> CFG might be more expressive than the usual regular...
00:05:54 <oerjan> although as thue shows, you only need fixed strings and one buffer to be TC
00:06:35 <nio247> the idea is that if you can also include expressions for multiple buffers (i.e. a set of strings A -> a set of strings B, plus a set of subexpressions C that have to be equal among matches), then you can, for example, parse C code, populate a symbol table, and check if something is known or not at the same time.
00:07:40 <nio247> ... as opposed to writing a LL(*) parser for a superset of a language, and then doing semantic analysis (is this a variable name or a type name?) to discard invalid programs.
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00:11:46 <nio247> what I'm trying to do is take a turing-tarpit (a production-based string-rewriting system like Thue) and make it into something that is somewhat easier to use... except my flavor isn't much better in that regard either.
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03:06:34 <Bike> anyone here willing to explain to me how synchronous design in circuits works? i'm missing something easy i'm sure
03:08:41 <elliott> willing, not able
03:09:12 <Bike> i should have known :(
03:16:38 <kmc> obligatory "just ask your question"
03:17:19 <Bike> "how"
03:18:02 <kmc> what do you mean by "synchronous design"
03:18:04 <kmc> im probably not helpin
03:18:45 <Bike> i still don't understand how you like, synchronize everything to not happen all at once. it seems probably more complicated than doing "everything" on a clock posedge
03:26:31 <Fiora> um I'm not sure if it's what you mean, but like
03:26:44 <Fiora> register -> wires and transistors and stuff -> register
03:26:56 <Fiora> I think the idea is like. the clock is a period of time, and during that period of time, everything in the middle is "on"
03:27:04 <Fiora> and happens at once
03:27:19 <Fiora> but of course like, the signal takes time to travel down the middle, which happens during the clock, which isn't instant
03:27:24 <Bike> but like, then why would you worry about latency in an adder?
03:27:34 <Fiora> so like, towards the start of the clock, a wire near the end might have an interdeterminate state
03:27:37 <Fiora> *indeterminate
03:27:44 <Fiora> because the electricity hasn't propagated yet?
03:28:04 <Bike> yeah that's what i'm worried about
03:28:08 <Fiora> and the design rules and stuff ensure that the signal propagates to the end register before the clock ends, basically. so that it's not indeterminate
03:28:27 <Bike> oh, i see...
03:28:28 <Fiora> and so, you worry about latency because that limits how fast you can set your clock
03:28:31 <Bike> that makes sense.
03:28:35 <Bike> oh! yeah!
03:28:36 <Fiora> because you can't set your clock faster than the signal propagates?
03:28:39 <Bike> ok, yeah, cool
03:28:42 <Fiora> I think that's right.
03:28:44 <Bike> that helps
03:30:06 <Fiora> so I think when your FPGA thing tells you the clock rate of your design, it did the analysis and found the longest path? and then did math and stuff
03:30:23 <Bike> ok well i'm not as far as that yet, i'm doing the worrying myself >_>
03:30:28 <kmc> with FPGA it's more complicated though because it has these limited interconnects between different parts and it sometimes has to time-division multiplex them, i think
03:32:05 <kmc> and it has to decide where to put everything
03:32:16 <kmc> so it's not just adding up gate delays, but actually doing a really complex optimization problem
03:32:24 <Bike> yeah i think i'm still not sure how fpgas work
03:32:39 <Bike> my ide thing apparently lays things out in terms of logic gates, if only at some intermediate stage
03:33:00 <kmc> anyway note that you don't need clocks for pure combinational logic
03:33:23 <kmc> a pure logic gate (and any circuit of such gates with no feedback) will just have outputs that settle some amount of time after all the inputs have settled
03:33:41 <Bike> right, that's why we haven't learned any clocking in class :p
03:33:46 <kmc> where "settle" means that the voltage is in the "represents 0" or "represents 1" range for the logic family you're using
03:34:19 <kmc> (and really there are two sets of ranges, one for inputs and one for outputs)
03:34:43 <elliott> I should learn circuits by reading a lot of Lava code or something.
03:35:24 <kmc> so you need clocks when you have state, because you need to say when to update the state, presumably after the combinational logic has settled
03:35:32 <Bike> great, a/nother/ hdl
03:35:47 <kmc> (although there are some things that have state but no clocks, like a buffer with a schmitt trigger input)
03:35:51 <elliott> Bike: actually there's about six things called Lava.
03:35:58 <Bike> and i have the wrong xilinx chip.
03:36:13 <Bike> elliott: i'm guessing you mean the one related to circuits and haskell. who could say why i am making such a guess!
03:36:24 <elliott> Bike: I mean there are multiple circuit EDSLs for Haskell called Lava.
03:36:30 <zzo38> What HDL do you like anyways? I didn't like them perfectly due to other problem so I made up my own idea; what kind of feature would you want for HDL, anyways? I would like to know opinion of who does too
03:36:34 <elliott> there's York Lava, Kansas Lava, Chalmers Lava, probably others
03:36:35 * Bike sighs, closes everything
03:36:47 <Bike> back to biology, where the code is shitty but uniform
03:36:56 <mnoqy> ther'es a circuit edsl for scala too. what lanaguage DOESN'T have a circuit edsl at this point
03:37:00 <kmc> you can imagine making a whole processor — fetch, decode, execute, memory, writeback — as pure combinational logic, but the longest gate delay path through there will be really long
03:37:09 <Bike> kmc: right, right
03:37:14 <kmc> which is why pipelining was invented
03:37:32 <Bike> kmc: what fiora said makes this much easier for me to understand intuitively
03:37:34 <elliott> Bike: anyway I like 'em because VHDL and Verilog are so noisy and the Lavas seem nice and declarative (to varying degrees, I like the one that the Reduceron is built with most because it uses observable sharing so there's a lot less noise, even if it's kinda creepy).
03:37:35 <kmc> hooray
03:37:41 <zzo38> mnoqy: I don't know; perhaps INTERCAL? Is there one in Forth?
03:37:44 <kmc> I'm just throwing out things I know now :)
03:37:44 <Bike> and maybe sort of get the async stuff in neural models
03:38:21 <Bike> though i think i'm pretty far from implementing "An FPGA implementation of a polychronous spiking neural network with delay adaptation", soon the brain will be mine
03:38:49 <Bike> elliott: yeah verilog is pretty annoying, it just doesn't matter because i'm doing the circuitry equivalent of writing "convert fahrenheit to degrees" programs
03:39:23 <zzo38> I have used Verilog a little bit but I don't like it all that much; the others seem worse though.
03:39:36 <Bike> i suppose i shouldn't bother asking verilog-specific questions here since nobody seems to know it
03:39:49 <elliott> Bike: you can take a look at http://www.cs.york.ac.uk/fp/reduceron/memos/Memo23.txt. it's accessible even to me, person who knows nothing about circuits. maybe it'll just make you feel worse about having to use verilog though
03:39:54 <mnoqy> my experience with verilog is using it in conjunction with an ide to write a dumb pipelined processor for a schoolcourse
03:39:55 <Fiora> Bike: I basically know, like, my remnants of attempts to intuitively understand it -_-
03:40:17 <mnoqy> so i possibly have memories of a tiny bit of verilog
03:41:04 <Bike> elliott: why is this already talking about clock cycles... whatever, i'm just making a fuckin adder
03:41:30 <kmc> Bike: so I think the FPGA has its own clock, separate from any clocks you might built into your design
03:41:46 <Bike> hmmm
03:41:48 <kmc> things that look like pure combinational logic might still need to be implemented using clocks
03:41:53 <kmc> because of sharing those interconnects, etc
03:42:10 <Bike> there's one clock provided to me but i think others were mentioned
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03:43:26 <Bike> looking at the xilinx development internals has kind of soured me from learning about how the chip actually works, though >_>
03:44:46 <zzo38> I think you had better figure it out anyways so that it can be programmed by making a program in the FPGA to do it, so that you don't need the other computer to make it.
03:45:31 <Bike> What I mean is, zzo38, that to do that (which I would like to do,, in the abstract), I would essentially have to reverse engineer a few gigabytes worth of tools, which I don't really have the expertise or will to do.
03:45:56 <zzo38> Ask someone else to do.
03:46:18 <Bike> zzo38: Could you reverse engineer a few gigabytes worth of proprietary tools for me?
03:47:21 <zzo38> I don't think so, but I expect that maybe many people can try to do it together.
03:50:15 <zzo38> That includes anyone who has the file (I don't).
03:50:45 <Bike> you can get the system free, actually.
03:50:54 <Bike> free as in lack of beer, obviously
03:51:25 <zzo38> I don't have those FPGA though. Even if I had the program it won't help if I don't have FPGA as well.
03:52:20 <Bike> you don't need the physical board to figure out how the programs work.
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03:53:19 <zzo38> Having the physical board too would help
03:55:36 <zzo38> What kind of features would you intend to have in hardware programming languages?
03:57:12 <zzo38> To me, HWPL would be something like: TRIGGER .CLOCK SET .REGISTER TO .INPUT; or perhaps you wait it continuous instead of by edge, for example: LATCH .CLOCK SET .REGISTER TO .INPUT; CONNECT .REGISTER TO .OUTPUT;
03:57:38 <zzo38> What is your opinion of just this example at least?
03:58:14 <kmc> meanwhile in wired http://www.wired.com/wiredenterprise/2013/09/bitcoin-homeless/
03:59:12 <zzo38> Some commands might be: TRIGGER vector SET vector TO vector; LATCH bit SET vector TO vector; CONNECT vector TO vector; CONNECT vector TO vector WHEN bit; and so on.
04:03:16 <elliott> "And he can beef up this daily take with Bitcoin Tapper, a mobile app that doles out about 0.000133 bitcoins a day — a couple of pennies — if he just taps on a digital icon over and over again." kill everyone
04:06:56 <mnoqy> Bitcoin beats the shit out of regular money
04:07:15 <elliott> what does it mean that 600k homeless people in the US seems surprisingly low to me
04:07:39 <zzo38> mnoqy: I am just using regular money though, just Canadian coins and bills
04:08:08 <mnoqy> zzo38: i bet it doesn't have any shit in it. you can thank bitcoin for that.
04:08:41 <zzo38> OK
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04:18:29 <Bike> "Each numeric type contains exactly one value." yeah this is grand
04:28:00 <zzo38> Bike: What are you refering to?
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05:07:10 <Bike> some bytes
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05:14:33 <Jafet> kmc: .oO( https://medium.com/funny-stuff/d7e5d14065f1 )
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05:17:12 <Bike> that's hard to read.
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05:18:43 <Jafet> Only the third part is relevant.
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05:19:21 <Bike> to?
05:19:25 <Bike> or the homelessness thing.
05:19:30 <kmc> buttcoin
05:20:22 <Bike> i think it's worth noting that "paid to hit a button for advertisers" is, still, pretty much an actual improvement
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05:51:21 <kmc> neat that numpy lets you get the elements of x which are less than 4 as x[x < 4]
05:51:26 <kmc> because x<4 is an array of bools
05:53:35 <zzo38> Ah, that is interesting, and is a good idea to use array of bools like this.
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14:23:26 <Roujo> @ask Gregor elliott kicked HackEgo on Friday, could you bring it back in the channel? Thank you! =)
14:23:26 <lambdabot> Consider it noted.
14:23:59 <Gregor> Nope. Manifest destiny.
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14:58:54 <Roujo> Gregor: Okay =P
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17:12:20 <zzo38> Why did elliott kick HackEgo on Friday?
17:12:47 <Bike> gone power-mad
17:13:57 <elliott> it was being used for multi-bot spam :p
17:15:00 <zzo38> I suppose you can still access it private anyways
17:15:08 <zzo38> Let's see
17:15:28 <zzo38> Yes it still works
17:17:01 <zzo38> And things like `list and so on can still be typed into the channel even if HackEgo no longer responds; you will have to filter on the client-side instead, now.
17:17:45 <zzo38> When I told you that at first, you didn't like it; now what do you think?
17:17:52 <zzo38> See?
17:18:56 <Bike> WHAT DO YOU THINK OF MY IDEAS NOW, ACADEMY?? MWAHAHAHAHAHA *zzo surrounded by lightning*
17:25:59 <Bike> "Hopefully VIS will get it working soon, but they don't care (or know) much about linux. " ausdfahisdfnqfoiasdf
17:26:31 <Bike> i didn't even know that IT people not knowing some unix was a thing. what a fool i am.
17:39:55 <pikhq> It's a pretty common thing TBH.
17:40:39 <coppro> yeah
17:40:39 <Bike> yeah.
17:40:56 <Bike> i don't think this problem is even linux-specific though, so i'll have to find a windows computer to test on. siiiigh
17:44:59 <Bike> i wish my department and the EECS department just shared tech support. what's the fuckin point of splitting it up
17:56:06 <coppro> they don't trust each other
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18:04:00 <AnotherTest> Hi
18:09:58 <Jafet> The computer science department, as a rule, never uses the same tech support.
18:10:30 <Bike> well i mean, i want the CS department's tech support to take over everyone else's, for hopefuly obvious reasons.
18:11:20 <Jafet> The other departments, as a rule, never use the computer science department for tech support.
18:11:25 <Bike> but whyyyyy
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18:51:45 <zzo38> What should I call the command to tell it that a label refers to a vocabulary entry? (It is like DW but it sets the internal vocabulary flag in the compiler)
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19:38:02 <Sgeo_> Played Mafia IRL last night. Couldn't stop cracking up when I was maf, still managed to win that round
19:39:20 <oerjan> it's ok as long as it's not evil laughter
19:46:28 <myname> i hate it when other people have ideas that i'd love to have
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20:18:39 <fizzie> "Recommended For You" "The New Nordic Diet - from Gastronomy to Health" ... I don't know about this, Coursera.
20:22:42 <oerjan> the lutefisk diet, guaranteed to lose weigth as long as you eat nothing else.
20:22:48 <oerjan> *weight
20:27:57 <Gregor> Corpses shed weight pretty fast.
20:28:30 <oerjan> some people _may_ have claimed the word "else" is redundant there.
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20:50:22 <kmc> can i eat lutefisk and hákarl
20:54:34 <oerjan> i'm sure you _can_
20:55:00 <Sgeo_> oerjan: I was laughing when the narrator announced who was killed off
20:55:41 <coppro> great narrators are awesome
20:56:42 <oerjan> "Tragedy is when I cut my finger. Comedy is when you fall into an open sewer and die."
20:56:58 <kmc> i'm not sure I am physically capable of eating hákarl
20:57:00 <kmc> it sounds scary
20:57:14 <Sgeo_> They were joking that I was definitely either mafia or really liked death
20:57:21 <Sgeo_> Did I mention Mafia won?
20:57:32 <mnoqy> yes, you did
20:57:35 <oerjan> what's so scary, it's just rotten poisonous fish
20:57:44 <zzo38> oerjan: I have seen that quotation before
20:57:54 <zzo38> In a movie, that is how it is.
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20:59:00 <oerjan> zzo38: apparently it's "The 2,000 Year Old Man".
20:59:12 <oerjan> and Mel Brooks.
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20:59:50 <oerjan> well, i guess he'll never know.
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21:13:15 <kmc> the lights in my living room are now visualizing the operation of randomly chosen "turing machines" on a finite cyclic tape
21:13:52 <kmc> I wonder if there are heuristics for choosing interesting machines of this sort
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21:18:32 <kmc> Bike: it's often the case that the undergrad-run computing club has better stuff than the CS department or anyone else
21:23:01 <kmc> not in terms of hardware (since it's usually hand-me-downs) but in terms of competence and entertainment value
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21:30:49 <Bike> kmc: the CS IT seems pretty good, they can wrangle the network printers and stuff. meanwhile the LUG is kinda stereotypical :p
21:38:11 <kmc> how so
21:39:20 <Bike> they had a sign up talking about how linux is better than windows because it's more secure but also just more fun
21:39:48 <Fiora> were they having an argument about which distro is better as you passed by? xD
21:40:28 <kmc> stereotypes of linux user group: likes linux
21:40:30 <Bike> i didn't stick around, was only there to buy my fpga from the ieee people
21:40:31 <Bike> yes
21:43:01 <Bike> anyway: «Decaf design's initiative aims for global synergy of design area's to "Green" an actual product, while seeking execution by exposure to producers and investors - San Francisco"
21:43:05 <Bike>
21:43:55 <elliott> area's
21:44:21 <Phantom_Hoover> Bike, are they making coffe?
21:44:23 <Phantom_Hoover> *coffee
21:45:00 <olsner> sounds like they're trying to obfuscate that they haven't figured out what they're doing yet
21:45:53 <Bike> they retweeted a reply i made that seemingly has nothing to do with any of that, and had already retweeted a bunch of weird stuff from strangers multiple times, so i just reported them as spam
21:45:59 <Bike> this will be very effacious i'm sure
21:46:19 <Bike> efficacious* i dunno i love that word
21:48:58 <oerjan> ecoffeacious
21:49:15 <Gregor> Echo-feces-ous
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23:55:32 <Bike> http://c431376.r76.cf2.rackcdn.com/38376/fnins-07-00014-HTML/image_m/fnins-07-00014-t001.jpg hardest of the core
23:56:17 <kmc> huh LUTs as RAM
23:56:24 <kmc> what did you compile
23:56:59 <Bike> not me yet :( it's a neural simulator, most of the ram is axonal properties
23:57:52 <olsner> hmm, I read neural stimulator and thought you were building some kind of mind-computer interface
23:58:48 <oerjan> what you are seeing is just the escaped AI simulating Bike to throw us off while it conquers the world.
←2013-09-20 2013-09-21 2013-09-22→ ↑2013 ↑all